Self-Aligned HJFET Gate Stack Overlap Reduces Series Resistance
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Solution Overview
Problem
Conventional Si heterojunction field effect transistors (HJFETs) have limitations in minimizing functional underlap, leading to higher source/drain series resistance and larger channel lengths, which are not ideal for small and medium-sized displays.
Innovation Solution
The development of overlapping HJFET structures where the gate stack overlaps onto source/drain stacks, or vice versa, with sub-lithographic spacer lengths, reducing the functional underlap and series resistance, and allowing for more compact devices with fewer lithography steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional HJFET structures are used with separate gate and source/drain regions, then fabrication process is simpler, but functional underlap is larger leading to higher source/drain series resistance
Solution Approach 1:
The gate stack and source/drain stacks are merged into a single overlapping structure where the gate stack is deposited directly onto the source/drain stacks, eliminating the need for separate alignment steps and reducing functional underlap. This combining of structures achieves both lower series resistance and simplified fabrication.
Solution Approach 2:
The source/drain stacks are formed first as a preliminary step, providing a foundation for the subsequent gate stack deposition. This preliminary action enables the gate stack to be deposited directly onto the source/drain regions, creating the overlapping configuration that reduces functional underlap before final patterning.
2Length of moving object
If conventional HJFET structures are used, then channel length is larger, but source/drain series resistance is higher
Solution Approach 1:
The invention transitions from a planar, non-overlapping layout to a three-dimensional overlapping structure where the gate stack vertically overlaps the source/drain stacks. This dimensional change allows for reduced functional underlap and lower series resistance while maintaining appropriate channel length control through lateral positioning.
3Reliability
If overlapping structures are implemented, then source/drain series resistance is minimized, but fabrication complexity increases
Solution Approach 1:
The overlapping gate and source/drain stacks form a self-aligned structure where the deposition process automatically creates the overlapping configuration without requiring additional alignment steps. The structure serves itself by using the source/drain stacks as the substrate for gate stack deposition, eliminating complex alignment procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in minimized source/drain series resistance, more compact channel devices, and lower fabrication costs, making it suitable for small and medium-sized displays such as cell phones and tablets.
Implementation Method 1
The width of the depletion region associated with the junction formed between the gate region and the base semiconductor substrate within the channel region is modulated by the voltage bias applied to the gate electrode. The gate electrode of the JFET is therefore effective in modulating the current that flows between the drain electrode and the source electrode.
Data Source
AI summary
A junction field effect transistor (JFET) comprises an insulating carrier substrate, a base semiconductor substrate formed on the insulating carrier substrate and a gate region formed on the base semiconductor substrate. The gate region forms a junction with the base semiconductor substrate. The JFET further comprises a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region and a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region. A gate stack is deposited on the gate region, a first source/drain stack is deposited on the first source/drain region and a second source/drain stack is deposited on the second source/drain region. At least one of the gate stack, first source/drain stack and second source/drain stack overlaps onto another one of the gate stack, first source/drain stack and second source/drain stack.