HLII Silicon Interposer Interface for Chiplet Data Transmission
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Solution Overview
Problem
The silicon interposer interconnection requires large-scale high-speed input/output (I/O) interconnection between heterogeneous chiplets, necessitating a different interface design than traditional PCB or SIP integration, which poses challenges for data transmission efficiency and power consumption.
Innovation Solution
An HLII architecture is designed for silicon interposer interconnection, comprising a physical layer (PL) and a link layer (LL), where the LL receives signals from the chiplet, performs data conversion, and controls the PL, enabling high-speed data transmission between chiplets through the silicon interposer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional high-speed interface design is used for silicon interposer interconnection, then the interface design is simple and familiar, but data transmission efficiency is insufficient and power consumption is high
Solution Approach 1:
The interface is divided into two distinct layers: Physical Layer (PL) for signal transmission and Link Layer (LL) for data conversion and control. This segmentation allows each layer to be optimized independently, with the LL handling protocol conversion and the PL handling high-speed signal transmission, thereby improving transmission efficiency while reducing overall power consumption through specialized optimization.
Solution Approach 2:
The Link Layer acts as an intermediary between the chiplet's logical resources and the Physical Layer. It performs data conversion on data signals and controls the PL, enabling efficient protocol translation and signal conditioning that optimizes both transmission efficiency and power usage in the silicon interposer interconnection.
2Speed
If traditional interconnection interface is used, then the design is simple, but it cannot meet large-scale high-speed I/O interconnection requirements between heterogeneous chiplets
Solution Approach 1:
The interface architecture is segmented into Physical Layer (PL) and Link Layer (LL), where the PL handles high-speed signal transmission and the LL handles data conversion and control functions. This segmentation enables the system to achieve large-scale high-speed I/O interconnection while managing complexity through layered design, allowing each layer to be optimized independently for its specific function.
Solution Approach 2:
The HLII architecture provides a universal interface design that can handle heterogeneous chiplet interconnections through the Link Layer's data conversion capabilities. The PL-LL structure serves multiple functions including signal transmission, protocol conversion, data conversion, and control, making it adaptable to various chiplet types and interconnection requirements.
Data Source
AI summary
A high-speed low-latency interconnect interface (HLII) for silicon interposer interconnection is provided. The HLII is configured to perform large-scale input/output (I/O) interconnection on a silicon interposer, and includes a physical link (PL) and an LL (LL). The LL receives a data signal, a configuration signal, and a control signal of logical resource inside a chiplet, and can complete data conversion, parity check, training, channel repair, instruction stream generation, and other functions for the PL. The PL receives and transmits a data signal converted by the LL. The PL includes a high-speed I/O port, a first input first output (FIFO), and related control logic. The high-speed I/O port of the PL is compatible with both a double date rate (DDR) transmission mode and a single data rate (SDR) transmission mode.