Hole-Current Erase Verification for Uniform 3D Memory Erasure
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Solution Overview
Problem
In three-dimensional non-volatile memory devices, the variation in erase speed along the length of memory pillars leads to faster-to-erase cells becoming over-erased, causing negative consequences due to current technology's inability to differentiate and manage erase rates effectively.
Innovation Solution
Implement a dual erase verify test with different levels to identify fast and slow-to-erase memory cells, inhibiting further pulses to fast cells while allowing additional pulses for slow cells, thereby optimizing the erase process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single erase verify test is used for all memory cells, then the erase process is simple and fast, but faster-to-erase cells become over-erased while slower-to-erase cells cannot be properly managed
Solution Approach 1:
The patent segments the erase verify process into multiple distinct test levels (first erase verify level and second erase verify level) that are applied at different stages. The first level detects fast-to-erase cells after initial erase pulses, while the second level detects slow-to-erase cells after additional pulses. This segmentation allows different cell types to be managed separately, preventing over-erasure of fast cells while ensuring complete erasure of slow cells.
Solution Approach 2:
The patent applies different verify test levels to different subsets of memory cells based on their erase characteristics. Fast-to-erase cells are identified and handled with the first verify level, while slow-to-erase cells are handled with the second verify level. This local differentiation ensures that each cell type receives appropriate verification treatment, improving overall erase reliability without sacrificing speed.
2Reliability
If multiple erase pulses are applied to ensure complete erasure, then all memory cells can be erased, but faster-to-erase cells become over-erased and suffer negative consequences
Solution Approach 1:
The patent implements feedback mechanisms through erase verify tests that continuously monitor the erase status of memory cells. After each erase pulse, the first erase verify test checks for fast-to-erase cells and the second erase verify test checks for slow-to-erase cells. This feedback allows the system to stop applying pulses to fast cells once they are sufficiently erased, while continuing to apply pulses to slow cells until they are also fully erased, thus preventing over-erasure damage.
Solution Approach 2:
The patent performs preliminary identification of fast-to-erase cells using the first erase verify test after initial erase pulses. By detecting these cells early and inhibiting further pulses to them, the system prevents over-erasure before it can cause damage. This preliminary action allows the system to then focus additional pulses only on slow-to-erase cells that need them.
3Reliability
If erase verify tests are performed frequently to monitor cell status, then erase uniformity is maintained, but the time required for the erase process increases
Solution Approach 1:
The patent applies partial verification action by using two selective verify tests rather than a single comprehensive test. The first erase verify test is applied partially to detect fast-to-erase cells after initial pulses, and the second erase verify test is applied partially to detect slow-to-erase cells after additional pulses. This partial action approach maintains erase uniformity while minimizing the total time required compared to continuous comprehensive verification.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures uniform erase completion across memory pillars, preventing over-erasure of faster cells and improving overall erase efficiency.
Implementation Method 1
In one embodiment, a first erase verify test that uses a first erase verify level is used to detect fast-to-erase memory cells. In one embodiment, a second erase verify test that uses a second erase verify level is used to detect slow-to-erase memory cells.
Data Source
AI summary
An apparatus is provided that includes a memory cell coupled to a word line, and a control circuit coupled to the word line and the memory cell. The control circuit is configured to perform an erase operation on the memory cell by applying an erase pulse to the word line, performing a first erase verify test on the memory cell to sense a hole conduction current, and performing a second erase verify test on the memory cell to sense an electron conduction current.