Hole Systematic Fault Rate Calculation for Semiconductor Yield
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Solution Overview
Problem
Current semiconductor integrated circuit manufacturing technologies fail to enhance yield effectively by not satisfying minimum design rule values, necessitating the development of a method to improve yield through optimized layout design and fault rate analysis.
Innovation Solution
A method involving determining experimental values for hole distances, forming test patterns, calculating fault rates, and converting systematic fault rates into per-unit hole length to optimize layout design and enhance yield, utilizing a system with storage and calculation units to process and analyze fault rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If minimum design rule value is used in layout design, then manufacturing complexity is reduced, but yield deteriorates due to systematic faults
Solution Approach 1:
The patent performs preliminary classification of faults into systematic and random categories before yield calculation. By预先 identifying systematic faults through test pattern analysis and establishing correction values in advance, the method enables accurate yield prediction and optimization without requiring complex iterative adjustments during manufacturing
Solution Approach 2:
The patent introduces a correction value parameter that adjusts the systematic fault rate based on actual test results. This parameter modification allows the yield calculation to account for systematic faults dynamically, transforming the fixed minimum design rule approach into an adaptive system that compensates for manufacturing variations
2Reliability
If recommended rule value higher than minimum design rule is used, then yield is enhanced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent applies partial correction by focusing only on systematic faults rather than addressing all possible manufacturing variations. By calculating correction values only for identified systematic fault patterns and applying them selectively to layout design, the method achieves yield enhancement without the full complexity of comprehensive design rule expansion
3Device complexity
If systematic fault rate is not differentiated from random fault rate, then analysis simplicity is maintained, but measurement precision deteriorates
Solution Approach 1:
The patent segments the total fault rate into two distinct components: systematic fault rate and random fault rate. This segmentation is achieved through test pattern analysis where systematic faults (reproducible patterns) are separated from random faults (stochastic occurrences), enabling precise measurement and targeted correction of each component
Solution Approach 2:
The patent establishes a feedback mechanism where test pattern results are used to calculate correction values that are then applied to refine the systematic fault rate estimation. This iterative feedback loop continuously improves measurement precision by comparing predicted versus actual yields and adjusting the systematic fault characterization accordingly
Data Source
AI summary
A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.