Hollow Trench Isolation with Strain Inducing Layer
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Solution Overview
Problem
As transistors in integrated circuits shrink, the reduced distance between them leads to undesired electric field interference and leakage currents, degrading performance and increasing power consumption, which becomes uneconomical and heats the chip, necessitating improved isolation and carrier mobility techniques.
Innovation Solution
A shallow trench isolation is implemented with a hollow trench and a thin strain-inducing material, such as silicon nitride, deposited on the sidewalls to induce strain in the channel region of transistors, enhancing carrier mobility and reducing capacitance between adjacent transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are scaled down to increase density, then circuit complexity and switching speed are improved, but leakage currents and electric field interference between adjacent transistors increase
Solution Approach 1:
The isolation structure is segmented into multiple functional layers: a hollow trench providing physical separation, sidewall strain layers for carrier mobility enhancement, and cap layers for stress management. This segmentation allows each layer to perform its specific function independently, achieving both isolation and performance enhancement.
Solution Approach 2:
The hollow trench acts as an intermediary structure between adjacent transistors, providing physical and electrical isolation. The strain-induced layers serve as intermediary elements that mediate between the isolation requirement and the performance enhancement requirement by introducing controlled stress fields.
2Reliability
If traditional filled trench isolation is used, then isolation between transistors is achieved, but capacitance between adjacent transistors increases
Solution Approach 1:
The conventional dielectric fill material is completely removed from the trench, extracting the source of high capacitance. The trench is left hollow, containing only the essential strain-induced layers on the sidewalls, thereby minimizing capacitance while preserving isolation functionality.
Solution Approach 2:
The hollow trench structure can be viewed as an extreme form of porosity, where the isolation region contains air or vacuum instead of solid dielectric material. This porous approach minimizes the dielectric constant and thus reduces capacitance between adjacent transistors.
3Reliability
If strain inducing layers are added to improve carrier mobility, then transistor performance is enhanced, but device complexity increases
Solution Approach 1:
The isolation structure and strain induction function are merged into a single integrated system. The sidewall layers of the hollow trench serve dual purposes: providing structural definition for the isolation trench and simultaneously acting as strain-induced layers to enhance carrier mobility in the adjacent transistor channels.
Solution Approach 2:
The hollow trench structure with sidewall layers serves multiple functions simultaneously: electrical isolation between transistors, strain induction for carrier mobility enhancement, and potential stress management through cap layers. This multi-functionality reduces the need for separate structures for each function.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves transistor performance by increasing carrier mobility and reducing power dissipation while maintaining effective isolation, allowing for lower supply voltages and reduced heat generation.
Implementation Method 1
The strain inducing layers induce either a tensile or compressive strain on the channel region of the transistor, according to the type of the transistor, and in so doing improve carrier mobility in the channel region
Implementation Method 2
A shallow trench isolation between transistor regions is left substantially hollow, thus reducing a capacitance between adjacent transistors
Data Source
AI summary
A shallow trench isolation is formed in a semiconductor substrate adjacent a MOS transistor. The shallow trench is filled with a fill material while other processing steps are performed. The fill material is later removed through a thin well etched into layers above the trench, leaving the trench hollow. A thin strain inducing layer is then formed on the sidewall of the hollow trench. The well is then plugged, leaving the trench substantially hollow except for the thin strain inducing layer on the sidewall of the trench. The strain inducing layer is configured to induce compressive or tensile strain on a channel region of the MOS transistor and thereby to enhance conduction properties of the transistor.