Host-Side Peripheral Interface Circuit Phase Adjustment
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Solution Overview
Problem
Conventional communication interfaces between hosts and peripheral devices face challenges in signal synchronization, requiring complex clock path analysis and additional phase-locked loops to ensure smooth communication, which can lead to inaccuracies and delays in data transfer.
Innovation Solution
A peripheral interface circuit at the host side includes a bus clock signal generator and a data register, where the bus clock signal is generated based on a host clock signal and adjusted to account for phase-asynchronous data output from the peripheral device, using a phase shift control module to optimize data accuracy and throughput by adjusting the bus clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If two separate paths are used to generate host clock signal and bus clock signal based on source clock signal, then the host and peripheral device can operate independently, but additional phase-locked loop is required and complex clock path analysis must be performed to ensure proper synchronization
Solution Approach 1:
The patent merges the host clock signal generation and bus clock signal generation into a single integrated path. The bus clock signal generator uses the host clock signal as its input, eliminating the need for separate clock paths and additional phase-locked loops. This integration simplifies the overall clock management while maintaining independent operation capabilities through software-controlled phase adjustment.
Solution Approach 2:
The patent changes the parameter relationship between host clock signal and bus clock signal from fixed synchronous generation to adjustable phase-asynchronous generation. By allowing the bus clock signal to have variable phase relationships with the host clock signal, the system can adapt to different timing requirements without adding complex synchronization hardware.
2Measurement precision
If phase-locked loop is added to generate bus clock signal, then synchronization accuracy can be improved, but device complexity and potential for inaccuracies increase
Solution Approach 1:
The patent extracts the phase-locked loop from the clock generation path and replaces it with a simpler phase adjustment mechanism. Instead of using hardware-based phase-locked loops to synchronize clocks, the system uses software-controlled phase adjustment of the bus clock signal relative to the host clock signal, achieving synchronization without the complexity and potential inaccuracies of traditional phase-locked loops.
Solution Approach 2:
The patent substitutes the mechanical/electronic phase-locked loop system with a digital phase adjustment approach. Rather than using analog phase-locked loop circuitry, the system adjusts clock phases through digital control mechanisms, eliminating the hardware complexity and associated inaccuracies while maintaining synchronization precision.
3Reliability
If complex clock path analysis is performed to generate host clock signal and bus clock signal, then communication smoothness can be ensured, but time consumption and processing overhead increase
Solution Approach 1:
The patent performs preliminary phase adjustment of the bus clock signal before data transmission begins. By pre-adjusting the phase relationship between host and bus clock signals based on predetermined timing characteristics, the system ensures smooth communication without requiring complex real-time clock path analysis during data transfer operations.
Solution Approach 2:
The system uses self-service timing mechanisms where the bus clock signal generator automatically adjusts phase based on the host clock signal without requiring external intervention or complex analysis. The predetermined timing characteristics allow the system to self-synchronize, eliminating the need for time-consuming clock path analysis while maintaining communication reliability.
Data Source
AI summary
A peripheral interface circuit at host side and an electronic system using the same is disclosed. The peripheral interface circuit has a bus clock signal generator and a data register. The bus clock signal generator outputs a bus clock signal based on a host clock signal to be conveyed to a peripheral device via an interface bus as a reference for the peripheral device to output data. The data register receives the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal. The bus clock signal generator adjusts the bus clock signal based on how the host clock signal is phase-asynchronous to the data output from the peripheral device and retrieved at the host side in accordance with the host clock signal.