Host Voltage Reference for Reduced Signal Memory Interfaces
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Solution Overview
Problem
High-speed memory interfaces, such as DDR, face challenges in supporting reduced signal levels due to voltage mismatches between hosts and memory devices, where the host operates at a lower voltage than the memory device, leading to unsupported signal levels.
Innovation Solution
Incorporating additional electrical contacts in the host to provide a controllable voltage reference (VREF) that can be optimized for reduced signal levels, allowing the host to symmetrically drive signals around the VREF, and using calibration circuits to set pull-up and pull-down values, ensuring adequate voltage margins for signal capture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the VREF is fixed at one-half of the DRAM voltage to match similar operating voltages, then the interface operates reliably when DRAM and host use similar voltages, but the signal level is not supported when the host uses a lower voltage process
Solution Approach 1:
The patent applies the dynamics principle by making the VREF voltage adjustable rather than fixed. The host can dynamically set the VREF to different voltage levels (e.g., 600mV or 750mV) depending on whether it operates at reduced signal levels or standard voltage levels, enabling the same interface to adapt to different voltage environments and process technologies
Solution Approach 2:
The patent implements parameter changes by allowing the VREF voltage parameter to be modified based on operating conditions. When the host uses a lower voltage process (e.g., 1.1V), the VREF is adjusted to a lower value (e.g., 600mV), and when using standard voltage (e.g., 1.5V), the VREF is set to the standard value (e.g., 750mV), thus changing the electrical parameters to match different operating scenarios
2Use of energy by moving object
If the host uses a lower voltage process to reduce power consumption, then energy efficiency improves, but the signal level becomes incompatible with the DRAM receiver requirements
Solution Approach 1:
The patent introduces an intermediary mechanism by using the VREF as a mediating voltage reference that bridges the gap between the host's lower voltage signals and the DRAM's higher voltage requirements. The VREF is set to an intermediate value that allows proper signal level comparison and capture, enabling the host to operate at lower voltages while maintaining reliable communication with the DRAM
3Adaptability or versatility
If additional electrical contacts are added to provide controllable VREF, then voltage compatibility and reduced signal level support are enabled, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the additional electrical contact to serve multiple functions: it provides the controllable VREF for reduced signal level operation, maintains compatibility with standard voltage operation when not used, and enables future-proofing for various voltage scenarios. This multi-functional design justifies the added complexity by providing broad adaptability
Data Source
AI summary
Embodiments of the invention are generally directed to systems, methods, and apparatuses for reduced signal level support for memory devices. In some embodiments, a host includes one or more additional electrical contacts to provide a controllable voltage reference to a memory device. The host may also include driver circuitry to provide a driver signal to the memory device. In some embodiments, the driver signal is substantially symmetrical around the controllable voltage reference.