HOT Substrate Boundary Defect Reduction via Amorphization
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Solution Overview
Problem
Conventional hybrid orientation technologies for integrated circuits introduce defects and discontinuities that limit transistor density and scaling, particularly in deep submicron fabrication methods, making them unsuitable for high-performance applications like SRAMs and logic gates.
Innovation Solution
A method using a directly bonded silicon substrate with a (110)-oriented silicon layer on a (100)-oriented silicon wafer, followed by double ion implantation to amorphize NMOS regions and a solid phase epitaxial process to form (100)-oriented silicon, reducing lateral boundary spread and preventing crystal defects, enabling the creation of a hybrid orientation substrate compatible with deep submicron CMOS ICs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If amorphization ion implant followed by recrystallization anneal is performed in conventional HOT, then regions with (100)-oriented silicon and (110)-oriented silicon are formed to maximize carrier mobility, but discontinuities and defects are introduced at the lateral boundaries between oriented silicon regions
Solution Approach 1:
The patent performs complete amorphization of the DSB layer in NMOS regions before recrystallization, which prevents lateral spread of the boundary region between (110)- and (100)-oriented silicon during the subsequent SPE process. This preliminary complete amorphization action eliminates the morphology defects that would otherwise form at lateral boundaries
Solution Approach 2:
The patent changes the recrystallization temperature parameter to be below the onset temperature for lateral spread of the amorphous region. By controlling the temperature parameter during SPE, the boundary region lateral spread is minimized while still achieving complete recrystallization of the amorphized DSB layer
2Manufacturing precision
If recrystallization is performed after shallow trench isolation process in conventional HOT, then stable defects are introduced at STI boundaries, but high temperature anneals over 1250° C. are required to eliminate these defects
Solution Approach 1:
The patent performs complete amorphization of the DSB layer before STI processing, which creates a uniform amorphous region that recrystallizes cleanly during SPE. This preliminary action prevents the formation of stable defects at STI boundaries that would otherwise require high temperature annealing
Solution Approach 2:
The patent integrates the recrystallization process to occur continuously during the SPE step without requiring separate high temperature annealing after STI. The SPE process itself provides the controlled thermal environment needed for defect-free recrystallization while maintaining dimensional integrity
3Productivity
If conventional ATR is used for HOT substrate fabrication, then morphology regions are created that are not suitable for MOS transistors, but this limits transistor density in circuits requiring high density
Solution Approach 1:
The patent applies complete amorphization specifically in the NMOS regions where high transistor density is required, while leaving other regions unchanged. This localized treatment ensures that only the regions needing high-density MOS transistors have the optimized boundary morphology
Solution Approach 2:
The patent changes the amorphization completeness parameter in NMOS regions to eliminate the morphology region entirely. By achieving complete amorphization followed by controlled SPE, the boundary region lateral spread is reduced to enable high-density MOS transistor fabrication
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances carrier mobility for both NMOS and PMOS transistors, maximizing performance parameters and ensuring compatibility with advanced lithography nodes, thereby improving the operating speed and density of integrated circuits.
Implementation Method 1
Two amorphizing ion implants completely amorphize the DSB layer in NMOS regions
Implementation Method 2
A solid phase epitaxial (SPE) process is performed in which (100)-oriented silicon is formed in the NMOS regions using the (100)-oriented silicon in the substrate wafer for a seed layer
Implementation Method 3
A silicon dioxide layer is formed on a top surface of the DSB wafer to prevent crystal defects during subsequent recrystallization and annealing
Data Source
AI summary
Hybrid orientation technology (HOT) substrates for CMOS ICs include (100)-oriented silicon regions for NMOS and (110) regions for PMOS for optimizing carrier mobilities in the respective MOS transistors. Boundary regions between (100) and (110) regions must be sufficiently narrow to support high gate densities and SRAM cells. This invention provides a method of forming a HOT substrate containing regions with two different silicon crystal lattice orientations, with boundary morphology less than 40 nanometers wide. Starting with a direct silicon bonded (DSB) wafer of a (100) substrate wafer and a (110) DBS layer, NMOS regions in the DSB layer are amorphized by a double implant and recrystallized on a (100) orientation by solid phase epitaxy (SPE). Crystal defects during anneal are prevented by a low temperature oxide layer on the top surface of the wafer. An integrated circuit formed with the inventive method is also disclosed.