Hardware Software Communication Channel for FPGA Post-Silicon Validation
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Solution Overview
Problem
The validation of graphics processor chiplet hardware in a system-on-chip (SoC) is challenging due to the need for independent functionality without other SoC components, and existing methods lack efficient post-silicon validation techniques.
Innovation Solution
A technique is described that enables post-silicon validation of a graphics compute die (GCD) chiplet by interfacing it with a field-programmable gate array (FPGA) platform, allowing communication with a virtual simulated intellectual property (IP) core, configuration, enumeration, booting, and traffic facilitation between test silicon and a host test device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a large monolithic processor design is used, then integration is simplified, but manufacturing yield decreases due to increased probability of defects
Solution Approach 1:
The processor is divided into multiple independent chiplet modules that can be manufactured separately and then interconnected. Each chiplet is a smaller, manageable unit with its own functional components, allowing parallel manufacturing and testing. This segmentation reduces the probability of defects affecting the entire processor while maintaining integration through standardized interconnection interfaces.
2Ease of manufacture
If a monolithic processor design is used, then manufacturing process is simpler, but defect impact is magnified causing complete processor failure
Solution Approach 1:
The processor design is segmented into multiple chiplet modules that can be manufactured using standard processes and then assembled. Each chiplet can be independently tested and replaced if defective, preventing complete processor failure. The modular architecture maintains manufacturing simplicity through standardized interfaces and assembly procedures.
Solution Approach 2:
If a chiplet is found to be defective during testing or operation, only that specific chiplet needs to be replaced rather than discarding the entire processor. The modular design allows for easy removal and replacement of individual chiplet modules, recovering the functionality of the overall processor system with minimal waste.
3Reliability
If chiplet-based design is used, then manufacturing yield improves through replacement of defective chiplets, but device complexity increases due to interconnection requirements
Solution Approach 1:
The chiplet modules are designed with universal, standardized interconnection interfaces that can accommodate different chiplet types and configurations. These standardized interfaces simplify the interconnection complexity by providing consistent connection protocols and physical interfaces across all chiplet modules, making the system easier to manufacture and assemble despite the modular complexity.
4Device complexity
If existing validation methods are used for chiplet hardware, then validation process is simple, but validation effectiveness is insufficient for independent functionality
Solution Approach 1:
An intermediary validation system is introduced that includes a validation controller and test interface circuitry coupled between the chiplet under test and the host system. This intermediary provides specialized validation capabilities that can independently test chiplet functionality without requiring integration into the complete processor system, thereby improving validation effectiveness while managing complexity through a dedicated validation subsystem.
Data Source
AI summary
Described herein is a generic hardware/software communication (HSC) channel that facilitates the re-use of pre-silicon DPI methods to enable FPGA-based post-silicon validation. The HSC channel translates a DPI interface into a hardware FIFO based mechanism. This translation allows the reuse of the methods without having to re-implement the entire flow in pure hardware. The core logic for the transactor remains the same, while only a small layer of the transactor is converted into the FIFO based mechanism.