HTO Offset Spacers for Memory Junction Control
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Solution Overview
Problem
As semiconductor memory devices shrink in size, they face challenges with short channel behavior, reduced drain-source breakdown voltage, and increased column leakage current due to hot electrons and holes generated during programming, leading to transport program disturb (TPD) and reduced effective channel length, which affects programming efficiency and power consumption.
Innovation Solution
The solution involves forming memory devices with bit lines using spacers as an implant screen to control the lateral length of bit lines, allowing for higher energy and dose implants without short channel roll-off, thereby increasing the effective channel length and preventing TPD by forming deeper bit line junctions and blocking hot electron movement to adjacent cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to achieve higher circuit density, then device density is improved, but hot electrons generated during programming reach adjacent memory cells causing transport program disturb (TPD)
Solution Approach 1:
The patent introduces an intermediary structure (spacer or offset structure) between the bit line and adjacent memory cells. This intermediary physically blocks hot electrons generated during programming from reaching adjacent cells, thereby preventing TPD while maintaining the scaled-down device dimensions and high circuit density.
Solution Approach 2:
The patent segments the bit line structure by introducing a discontinuity or offset section. This segmentation creates a physical barrier that stops hot electron transport to adjacent cells. The bit line is divided into sections with different lateral positions, and the spacer further divides the structure to enhance the blocking effect.
2Quantity of substance
If device dimensions are scaled down, then circuit density is improved, but effective channel length is reduced affecting programming efficiency
Solution Approach 1:
The patent resolves the effective channel length issue by transitioning to a three-dimensional structure. The charge trapping dielectric stack extends vertically from the substrate surface, creating a vertical channel region. This vertical dimension compensates for the reduced horizontal channel length, maintaining effective channel length and programming efficiency while enabling smaller device footprints for higher density.
3Strength
If bit line implant energy and dose are increased to form deeper junctions, then drain-source breakdown voltage is improved, but short channel roll-off occurs in scaled devices
Solution Approach 1:
The patent applies local quality by creating asymmetric dopant distribution through the spacer structure. The spacer blocks dopants from reaching certain regions during implantation, creating locally different dopant concentrations. This results in deeper junctions in protected regions with higher breakdown voltage, while other regions maintain appropriate doping for preventing short channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the effective channel length, improves TPD characteristics, and increases drain-source breakdown voltage, reducing bit-line-to-bit-line current leakage and maintaining programming efficiency while minimizing power consumption.
Implementation Method 1
forming first bit lines in the semiconductor substrate under the first openings by using the first spacers as an implant screen
Implementation Method 2
hot electrons generated during programming a memory cell may reach adjacent memory cells and disturb programming the adjacent memory cells (e.g., TPD)
Data Source
AI summary
Memory devices having an increased effective channel length and/or improved TPD characteristics, and methods of making the memory devices are provided. The memory devices contain two or more memory cells on a semiconductor substrate and bit line dielectrics between the memory cells. The memory cell contains a pair of first bit lines and a pair of second bit lines. The first and second bit lines can be formed by an implant process using first and second spacers that have different lateral lengths from each other. The spacers can be used to offset the implants, thereby controlling the lateral lengths of the bit lines.