Hub Module for High Capacity Memory Subsystem Interleaving
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Solution Overview
Problem
Standardized memory modules optimized for low-end systems are inefficient when used in larger systems, leading to potential loss of efficiency and increased costs due to the need for custom designs to meet different system requirements.
Innovation Solution
A hub module is introduced that acts as a conduit between the memory controller and memory modules, allowing for daisy-chained configuration of memory chips with interleaved data distribution across multiple modules, maintaining data rate while reducing bus frequency and I/O ports, thus enabling efficient use of standardized modules across various system types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If standardized memory modules are used in larger systems, then manufacturing cost and design simplicity are improved, but system efficiency and performance deteriorate
Solution Approach 1:
The memory subsystem is segmented into multiple standardized memory modules, each functioning as an independent unit. The hub divides the system into manageable segments that can be independently configured and addressed, allowing standardized modules to be efficiently organized in larger systems without requiring custom designs.
Solution Approach 2:
The patent introduces a hierarchical addressing dimension with the hub as an intermediate level between the memory controller and memory modules. This adds a new dimension to the address space organization, allowing standardized modules to be accessed efficiently through the hub's ability to manage multiple modules simultaneously.
2Quantity of substance
If more memory modules are connected to support larger memory volume, then memory capacity is improved, but bus complexity and power consumption increase
Solution Approach 1:
The hub acts as an intermediary device between the memory controller and multiple memory modules. It manages data distribution and address routing, allowing multiple modules to be connected without proportionally increasing bus complexity. The hub absorbs the complexity of managing multiple modules while presenting a simplified interface to the memory controller.
3Quantity of substance
If data is distributed across multiple memory modules, then memory capacity and efficiency are improved, but data transfer time and latency increase
Solution Approach 1:
The hub merges multiple memory modules into a unified addressable space, combining their capacities while managing access efficiently. It consolidates data distribution across modules and can retrieve data from multiple modules in coordinated fashion, reducing the time penalty of distributed storage.
Solution Approach 2:
The hub enables continuous data transfer operations by managing data distribution across modules without interruption. It maintains steady data flow between the memory controller and distributed modules, minimizing idle time and keeping the data transfer pipeline full.
Data Source
AI summary
A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.