High-Voltage Generation Circuit Leakage Reduction

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Solution Overview

Problem

Conventional high-voltage generation circuits for nonvolatile semiconductor memory devices suffer from efficiency degradation due to charge leakage when driving output signals to high voltages, as the power-voltage driver transistors can turn on and allow accumulated charges to leak into the power source voltage, reducing the high voltage generation efficiency.

Innovation Solution

The proposed high-voltage generation circuit includes a power-voltage driver with specific MOS transistor configurations, such as an N-channel depletion MOS transistor and a P-channel MOS transistor, where the second MOS transistor is gated to remain off during high voltage output, and additional transistors are used to prevent forward bias and leakage current, ensuring the high voltage output is maintained efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If conventional power-voltage driver with depletion NMOS and PMOS transistors is used to drive output signal to high voltage, then high voltage generation is achieved, but charge leakage occurs from output node to power source voltage resulting in degraded high voltage generation efficiency

Engineering Contradiction:

Improvehigh voltage generation efficiencyVSAvoidcharge leakage

Core Design Contradiction:

PowerVSLoss of energy

Solution Approach 1:

The patent extracts and removes the problematic PMOS transistor (23) from the conventional power-voltage driver circuit. By eliminating this component that causes charge leakage, the circuit achieves improved high voltage generation efficiency without the energy loss associated with conventional designs.

Inventive Principle:

Principle #2Taking out (Extraction)

Solution Approach 2:

The patent segments the power-voltage driver into distinct functional components: a first depletion NMOS transistor (21) for primary voltage control and a second depletion NMOS transistor (25) for leakage prevention. This segmentation allows each transistor to be optimized for its specific function, with the second transistor specifically tasked with preventing charge leakage from the output node to the power source voltage.

Inventive Principle:

Principle #1Segmentation

2Use of energy by stationary object

If power source voltage is pulled down to lower voltage, then power consumption is reduced, but PMOS transistor turns on causing charge leakage and degraded high voltage generation efficiency

Engineering Contradiction:

Improvepower consumptionVSAvoidhigh voltage generation efficiency

Core Design Contradiction:

Use of energy by stationary objectVSPower

Solution Approach 1:

The patent changes the electrical parameters of the power-voltage driver by replacing the PMOS transistor with a second depletion NMOS transistor. This parameter change allows the circuit to operate efficiently at lower power source voltages without experiencing the turn-on behavior and charge leakage that plagues conventional PMOS-based designs.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs depletion mode NMOS transistors that can operate effectively across a wide range of voltage conditions. These transistors serve as robust, simple components that maintain circuit functionality even when power source voltage fluctuates, providing reliable operation without complex voltage regulation.

Inventive Principle:

Principle #27Cheap short-living objects (Disposable)

Data Source

PatentUS7372308B2High-voltage generation circuits and nonvolatile semiconductor memory device with improved high-voltage efficiency and methods of operating

Publication Date: 2008.05.13 SAMSUNG ELECTRONICS CO LTD

AI summary

A power-voltage driver circuit includes a first MOS transistor configured to turn a second MOS transistor off when a high-voltage generator provides a high voltage output. Related methods are also disclosed.