High-Voltage Device Gate Dielectric Leakage Mitigation
Solution Overview
Problem
High-voltage metal oxide semiconductor (HVMOS) devices experience current leakage due to the kink and snapback effects, which can damage the device, primarily because of the close proximity of the source and drain diffusion regions and the floating isolation structure, leading to parasitic current generation.
Innovation Solution
A high-voltage device is designed with a semiconductor substrate featuring a source diffusion region, a drain diffusion region, and a channel diffusion region, where a gate dielectric layer with a modified portion of opposite conductivity type is formed on the channel region, and a gate electrode is constructed to overlap partially with the modified portion, channel, and gate dielectric layer, enhancing the dielectric properties and increasing the threshold voltage to prevent current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the source diffusion region, drain diffusion region and isolation structure are placed close together to reduce device size, then device integration density is improved, but parasitic current is generated causing kink effect and snapback effect
Solution Approach 1:
The patent introduces a modified portion in the gate dielectric layer with different conductivity type (second conductive type) than the channel diffusion region (first conductive type). This creates a localized region with different electrical properties at the edge of the gate dielectric layer, forming a potential barrier that blocks parasitic current paths while maintaining the close spacing of source and drain regions for high integration density.
Solution Approach 2:
The modified portion acts as an intermediary structure between the gate electrode and the channel diffusion region. By introducing this intermediate layer with opposite conductivity type, the patent mediates the interaction between the gate and channel, preventing direct parasitic current flow while maintaining the desired device geometry.
2Reliability
If the threshold voltage is increased to prevent current leakage, then device reliability is improved, but the dielectric property of the gate dielectric layer deteriorates
Solution Approach 1:
Instead of uniformly modifying the entire gate dielectric layer, the patent applies the conductivity type change only to a modified portion at the edge region. This localized modification increases threshold voltage and blocks parasitic current while preserving the dielectric properties of the main gate dielectric layer, thus resolving the contradiction between reliability improvement and dielectric stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The modified gate dielectric layer and overlapping gate electrode structure effectively increase the threshold voltage and prevent current leakage, thereby mitigating the kink and snapback effects that could damage the high-voltage device.
Implementation Method 1
a gate dielectric layer with a modified portion of opposite conductivity type is formed on the channel region
Implementation Method 2
provide a local-increased parasitic capacitance at the edge of the gate dielectric layer which is located between the drain diffusion region and the source diffusion region
Data Source
AI summary
A high-voltage device includes a semiconductor substrate, a source diffusion region, a drain diffusion region, a channel diffusion region and a gate electrode. The source diffusion region and the drain diffusion region with a first conductive type are disposed in the semiconductor substrate. The channel diffusion region is disposed in the semiconductor substrate and between the source diffusion region and the drain diffusion region. The gate dielectric layer is disposed on the channel diffusion region and having a first modified portion with a second conductive type extending inwards from a first edge of the gate dielectric layer. The gate electrode is disposed on the gate electric layer, wherein the first modified portion, the gate electrode and the channel diffusion region at least partially overlap with each other.