High-Voltage Tolerant I/O Circuit Failsafe Biasing During Power Ramping
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Solution Overview
Problem
High voltage tolerant I/O circuits face device degradation and breakdown due to voltage stress during power supply ramping up and down, as conventional failsafe control and bias signal generators are ineffective in managing voltage differences during these transitions.
Innovation Solution
Incorporating a supply and failsafe detector component that generates a reference voltage to reduce device stress by shifting the voltage at which devices turn on or off, using a multiplexer to provide the appropriate reference voltage to transistors, and employing a voltage divider to adjust voltages, ensuring devices operate within their tolerance limits during power ramping scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If high voltage tolerant I/O circuits operate at higher voltage to interact with other chips at different voltage levels, then the I/O circuits can achieve voltage compatibility and communication capability, but the devices are subjected to voltage stress above their operating voltages resulting in device degradation and possible device breakdown
Solution Approach 1:
The patent introduces a failsafe detector as an intermediary component that monitors the I/O supply voltage and generates a control signal to prevent direct exposure of low-voltage devices to high-voltage stress. This mediator detects voltage conditions and activates protection mechanisms, allowing the I/O circuit to maintain voltage compatibility while protecting devices from degradation during voltage transitions.
2Reliability
If conventional failsafe control and bias signal generators are used, then basic protection is provided, but they are ineffective in managing voltage differences during power supply ramping up and down transitions
Solution Approach 1:
The patent employs dynamic control by detecting the actual I/O supply voltage level and adaptively adjusting the bias signals applied to transistors during power supply ramping transitions. Unlike static conventional failsafe circuits, this dynamic approach monitors voltage changes in real-time and modifies protection mechanisms accordingly, enabling effective management of voltage differences during both ramping up and ramping down transitions.
Solution Approach 2:
The failsafe detector provides feedback about the I/O supply voltage status to the bias signal generation circuitry. This feedback mechanism enables the system to sense voltage conditions and automatically adjust bias signals to maintain safe operating margins during transient conditions, making the protection system responsive to actual voltage transitions rather than relying on fixed conventional approaches.
3Adaptability or versatility
If devices operate at voltages above their threshold during power supply transitions, then voltage compatibility is maintained, but device stress increases leading to degradation and breakdown
Solution Approach 1:
The patent applies preliminary anti-action by proactively detecting voltage transitions before they cause harmful stress to devices. The failsafe detector anticipates potential over-voltage conditions during power supply ramping and pre-activates protection mechanisms by adjusting bias signals, thereby preventing voltage stress before it occurs rather than reacting after damage has been done.
Data Source
AI summary
A circuit provides fail safe protection of an input/output (I/O) circuit of a chip. The I/O circuit comprises an I/O pad connected to one or more other chips via an I/O bus. The circuit comprise a supply and failsafe detector component. The supply and failsafe detector component generates an I/O supply output signal. The I/O supply output signal has a low voltage value when the I/O supply voltage of the chip is below a medium voltage level and the I/O supply output signal having a high voltage value when the I/O supply voltage of the chip is above the medium voltage level. The medium voltage is above a threshold voltage of the transistor of the I/O circuit and below the high voltage value. The circuit uses the I/O supply output signal to provide a reference voltage as input to the transistor of the I/O circuit.