Crack Suppression Structure for HV Isolation Metal
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Solution Overview
Problem
Chemical mechanical polishing (CMP) processes in integrated circuit (IC) fabrication often result in dielectric cracks that can extend to underlying metal layers, leading to device failures and performance degradation, as dilute hydrofluoric acid can penetrate through cracks in the passivation layer to attack the top metal, causing voids and reliability issues.
Innovation Solution
A dielectric crack suppression structure comprising a crack-resistant dielectric layer, such as silicon nitride (SiN), is introduced between the passivation layer and the top metal layer of high voltage isolation components to prevent cracks from reaching the metal and protect it from chemical attacks during CMP, significantly reducing the incidence of device failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If CMP process is used to planarize the passivation layer stack, then surface flatness is improved, but dielectric cracks occur that extend to underlying metal layers
Solution Approach 1:
A crack-resistant dielectric layer is introduced as an intermediary barrier between the passivation layer and the top metal layer. This intermediate layer prevents cracks from propagating through the passivation layer to reach and attack the metal layer with hydrofluoric acid, thus resolving the contradiction between achieving surface flatness through CMP and preventing dielectric cracks.
Solution Approach 2:
The crack-resistant dielectric layer is deposited beforehand on the top metal layer to provide protective cushioning against crack propagation. This pre-established protective layer absorbs and stops crack energy before it can reach the metal, preventing the harmful effects of CMP-induced cracking.
2Object-generated harmful factors
If dilute hydrofluoric acid is used during CMP to clean the surface, then surface cleanliness is improved, but chemical attacks on top metal occur through crack penetrations
Solution Approach 1:
The crack-resistant dielectric layer serves as a protective intermediary between the hydrofluoric acid and the top metal layer. While the acid performs its cleaning function, any cracks that form in the passivation layer are stopped by this intermediate layer, preventing the acid from attacking and dissolving the metal layer.
3Reliability
If CMP process conditions are changed to reduce crack occurrence, then dielectric crack formation is reduced, but manufacturing complexity increases
Solution Approach 1:
Instead of modifying the complex CMP process parameters to prevent cracking, the solution extracts and removes the vulnerability by adding a dedicated crack-resistant dielectric layer. This approach addresses the crack issue through a structural modification rather than process optimization, avoiding increased manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of a crack-resistant dielectric layer effectively reduces the occurrence of dielectric cracks reaching the top metal, thereby enhancing the reliability and performance of high voltage isolation components by preventing chemical attacks and ensuring the integrity of the ICs, even under high voltage conditions.
Implementation Method 1
A dielectric crack suppression structure comprising a crack-resistant dielectric layer, such as silicon nitride (SiN), is introduced between the passivation layer and the top metal layer of high voltage isolation components to prevent cracks from reaching the metal
Implementation Method 2
The CMP process uses an abrasive and corrosive chemical slurry together with a polishing pad and retaining ring... The dynamic polishing head is rotated with different axes of rotation which removes material from the surface of the wafer
Data Source
AI summary
An integrated circuit (IC) includes a substrate having functional circuitry for realizing at least one circuit function configured together with at least one high voltage isolation component including a top metal feature above the substrate. A crack suppressing dielectric structure including at least a crack resistant dielectric layer is on at least a top of the top metal feature. At least one dielectric passivation overcoat (PO) layer is on an outer portion of the top metal feature.