High-Voltage MOS Device Field Oxide Sequence
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Solution Overview
Problem
The existing methods for manufacturing high-voltage MOS devices are costly and suffer from lateral diffusion of P-type device isolation regions, which affects junction profiles and prevents the use of poly field devices, hindering device shrinkage and increasing manufacturing complexity.
Innovation Solution
The method involves forming field oxide layers before implanting the device isolation diffusion region, and using a silicon nitride mask to define active areas simultaneously, allowing for ion implantation after field oxidation to prevent lateral diffusion and simplify the process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If P type device isolation diffusion region is implanted prior to field oxide formation, then device isolation is achieved, but lateral diffusion occurs during high-temperature thermal processes affecting junction profiles
Solution Approach 1:
The field oxide layers are formed in advance before implanting the device isolation diffusion region. This preliminary action ensures that the field oxide structure is established first, and subsequent ion implantation occurs after the field oxidation process, preventing lateral diffusion of the device isolation region during high-temperature thermal processes.
2Manufacturing precision
If multiple separate mask patterns are used to define channel, source/drain and device isolation regions, then precise region definition is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
A single silicon nitride mask pattern is used to simultaneously define the channel region, source/drain regions, and device isolation region. This merged approach consolidates multiple separate mask patterns into one, reducing manufacturing complexity and cost while maintaining precise region definition through the comprehensive coverage of the single mask structure.
Solution Approach 2:
The silicon nitride mask pattern serves multiple functions simultaneously: it defines the channel region, source/drain regions, and device isolation region all in one step. This multi-functional mask eliminates the need for separate mask patterns for each region, simplifying the overall manufacturing process.
3Reliability
If P type device isolation diffusion is formed before field oxide, then isolation structure is created, but dopant lateral diffusion hinders device shrinkage
Solution Approach 1:
Field oxide layers are formed in advance before device isolation diffusion implantation. This sequence prevents lateral diffusion of dopants that would otherwise occur during high-temperature thermal processes, allowing for more precise control of device dimensions and enabling device shrinkage while maintaining reliable isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, maintains higher doping concentrations, and allows for more flexible circuit design by preventing lateral diffusion of the device isolation region, enabling the use of poly field devices and M−1 field devices.
Implementation Method 1
performing an oxidation process to grow a first field oxide layer, a second field oxide layer and a third field oxide layer spaced-apart from one another on surface areas of the semiconductor substrate
Implementation Method 2
performing a first ion implantation process to form a drain doping region in the drain region and a source doping region in the source region
Data Source
AI summary
The present invention pertains to a high-voltage MOS device. The high-voltage MOS device includes a substrate, a first well, a first field oxide layer enclosing a drain region, a second field oxide enclosing a source region, and a third field oxide layer encompassing the first and second field layers with a device isolation region in between. A channel region is situated between the first and second field oxide layers. A gate oxide layer is provided on the channel region. A gate is stacked on the gate oxide layer. A device isolation diffusion layer is provided in the device isolation region.