High Voltage Tolerant Output Buffer With Substrate Biasing
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Solution Overview
Problem
Conventional IC packages face issues with power dissipation and potential gate oxide breakdown due to the inability of tristate buffers operating at 3.3 volts to tolerate 5 volt voltage levels, leading to inefficient high voltage tolerance and increased power consumption.
Innovation Solution
A high voltage tolerant output buffer circuit is designed with a substrate voltage control circuit and inverter, using transistors to maintain voltage between any two terminals of the output buffer circuitry within the supply voltage (VDD), preventing excessive voltage across transistors and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a tristate buffer operating at 3.3V is used in mixed mode operation with 5V circuits, then power dissipation is reduced, but the buffer cannot tolerate 5V voltage levels leading to potential gate oxide breakdown
Solution Approach 1:
The patent introduces an intermediary voltage level (VINT) between the 3.3V supply and 5V pad voltage. This intermediate voltage is generated by a voltage divider network (resistors R1 and R2) and used to bias the gate of the PMOS transistor, allowing the buffer to safely handle 5V inputs without exceeding the maximum voltage rating of the gate oxide while maintaining low power dissipation at 3.3V operation.
2Ease of operation
If the voltage at the pad rises to (VDD+|Vtp|) in a conventional pad driver, then the PMOS starts conducting, but current flows from pad to VDD causing power dissipation
Solution Approach 1:
The patent implements preliminary action by pre-biasing the gate of the PMOS transistor through the voltage divider network before the pad voltage rises to problematic levels. The gate is held at a predetermined intermediate voltage (VINT) that is higher than VDD but lower than VDD+|Vtp|, so when the pad voltage rises, the voltage difference across the PMOS is reduced, preventing excessive current flow and power dissipation.
3Reliability
If protection circuits are added to make the buffer 5V tolerant, then high voltage tolerance is achieved, but the circuit complexity increases
Solution Approach 1:
The patent achieves multi-functionality by using the same voltage divider network (resistors R1 and R2) that serves dual purposes: it generates the intermediate gate voltage for PMOS biasing during normal operation and also acts as a protection mechanism during 5V tolerance mode. This eliminates the need for separate protection circuits, maintaining simplicity while achieving both low-power operation and high-voltage tolerance.
Data Source
AI summary
A high voltage tolerant output buffer uses a substrate voltage control circuit to control the voltage at the substrate of the transistors in the output buffer. The circuitry of output buffer is such that the voltage between any two terminals of any of the transistors is not allowed to exceed the supply voltage of the output buffer. At the same time, the voltage at the source or drain of transistors of output buffer is not allowed to increase beyond its substrate voltage. The proposed circuit for output buffer can tolerate voltages higher than the voltage at which it is operated. The novel circuitry uses less hardware and prevents power dissipation in the circuit.