High Voltage Transistor Segmented Drift Region
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Solution Overview
Problem
High voltage semiconductor devices experience malfunctions and increased power loss due to parasitic capacitance and dV/dt surges in level shift circuits, leading to false signal transmission and inter-arm short circuits in high voltage ICs.
Innovation Solution
The structure of high voltage transistors is modified by forming two or more voltage blocking regions with a p−-region between them, where one n−-type region has a high impurity concentration drain diffused region connected to high electric potential wiring, and the other is at floating potential, reducing parasitic capacitance and output capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional level shift circuit is used in high voltage ICs, then the circuit can transmit control signals between different potential levels, but parasitic capacitance causes dV/dt surges leading to malfunctions and increased power loss
Solution Approach 1:
The voltage blocking region is divided into multiple segments separated by p-type regions. This segmentation isolates parasitic capacitance to specific segments, preventing dV/dt surges from affecting the entire circuit, thereby reducing power loss and improving signal transmission reliability
Solution Approach 2:
Parasitic capacitance is extracted and confined to isolated voltage blocking regions separated by p-type regions. By removing parasitic capacitance from the main signal path and confining it to isolated segments, the circuit avoids dV/dt surge-induced malfunctions and reduces power loss
2Speed
If voltage blocking regions are segmented with p-type regions, then parasitic capacitance is reduced and switching response speed improves, but device structure becomes more complex
Solution Approach 1:
The voltage blocking regions and p-type regions are merged into a unified transistor structure where the p-type regions serve dual purposes: they segment the voltage blocking regions to reduce parasitic capacitance while also forming part of the transistor's base region. This integration reduces structural complexity despite the segmentation
3Strength
If one n-type region has high impurity concentration drain diffused region connected to high electric potential, then voltage blocking capability is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
High impurity concentration is applied locally only to the drain diffused region of one n-type region that connects to high electric potential, while other regions maintain lower impurity concentrations. This localized quality enhancement provides targeted voltage blocking capability where needed most, reducing overall manufacturing precision requirements compared to uniform high impurity concentration throughout
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances switching response speed, reduces power loss, and minimizes malfunctions by making parasitic capacitance ineffective in voltage blocking regions, allowing for quicker discharge of output capacitance and shorter signal transmission delays.
Implementation Method 1
two or more voltage blocking regions of n−-type regions as drift regions of the high voltage transistor are separately formed with p−-region provided between the respective n−-type regions
Implementation Method 2
a drain diffused region with a high impurity concentration is formed in one n−-type region, while the other or the rest of the n−-type regions made to be at floating electric potentials. The drain diffused region is connected to high electric potential wiring
Data Source
AI summary
A high voltage semiconductor device is provided and includes an n−-type region encompassed by a p− well region and is provided on a p−-type silicon substrate. A drain n+-region is connected to a drain electrode. A p base region is formed so as to be separate from and encompass the drain n+-region. A source n+-region is formed in the p base region. Further, a p−-region is provided that passes through the n−-type region to the silicon substrate. The n−-type region is divided, by the p−-region, into a drift n−-type region having the drain n+-region and a floating n−-type region having a floating electric potential.