Self-Aligned High Voltage Transistor Channel Definition
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Solution Overview
Problem
Conventional CMOS processes are incompatible for forming high voltage (HV) transistors with short channel lengths, making it difficult to achieve low drain-to-source on-resistance (Rdson) and high breakdown voltage, which are essential for high performance LD transistors.
Innovation Solution
The solution involves a semiconductor device with a self-aligned effective channel length, where a doped channel well is disposed adjacent to the gate, and a doped drift well with a drift isolation region, allowing for precise control of the channel length and improved breakdown voltage through ion implantation, facilitating the integration of both low voltage and high voltage transistors on the same substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional CMOS processes are used to form HV transistors, then process compatibility is maintained, but channel length alignment precision deteriorates due to overlay issues
Solution Approach 1:
The gate electrode serves a dual function: as the functional gate structure and as a self-aligned hard mask for defining the channel well. The gate electrode's thick polysilicon structure provides excellent mask properties, eliminating the need for separate alignment processes and achieving precise channel length definition through self-alignment, thereby resolving the overlay issue while maintaining CMOS process compatibility
Solution Approach 2:
The gate electrode is designed to perform multiple functions: it serves as the operational gate for voltage control and simultaneously as a hard mask for the channel well formation process. This multi-functionality eliminates the need for additional alignment steps and process complexity, allowing precise channel length control within standard CMOS process capabilities
2Area of moving object
If thin gate electrodes are used, then device area is reduced, but manufacturing precision deteriorates as they cannot serve as effective hard masks
Solution Approach 1:
The gate electrode thickness is increased to a specific range (500-2000 nm) to transform it from a thin non-functional mask to a thick functional hard mask. This parameter change enables the gate to serve dual purposes: maintaining electrical functionality while providing sufficient thickness for effective photolithographic masking during channel well formation, thereby achieving precise manufacturing control
3Loss of energy
If channel length is reduced to achieve low Rdson, then power dissipation is minimized, but manufacturing precision becomes difficult to control due to process variations
Solution Approach 1:
The gate electrode automatically serves as the alignment reference for channel well formation through self-alignment. This eliminates sensitivity to process overlay variations, enabling precise channel length control even at very short lengths. The self-aligned mechanism ensures that the channel length is defined by the gate electrode position itself, not by separate alignment processes, thereby achieving manufacturing precision independent of process variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of HV devices with very short effective channel lengths and low Rdson, enhancing current density and reducing power dissipation, particularly suitable for deep sub-micron technologies beyond 0.35 μm.
Implementation Method 1
The solution involves a semiconductor device with a self-aligned effective channel length, where a doped channel well is disposed adjacent to the gate, and a doped drift well with a drift isolation region, allowing for precise control of the channel length and improved breakdown voltage through ion implantation
Data Source
AI summary
A device is disclosed. The device includes s substrate prepared with an active device region. The active device region includes a gate. The device also includes a doped channel well disposed in the substrate adjacent to a first edge of the gate. The first edge of the gate overlaps the channel well with a channel edge of the channel well beneath the gate. The first edge of the gate and channel edge defines an effective channel length of the device. The effective channel length is self-aligned to the gate. A doped drift well adjacent to a second edge of the gate is also included.