HVMOS Thick Gate Dielectric Drift Region Hot Carrier Injection
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Solution Overview
Problem
High-voltage metal-oxide-semiconductor (HVMOS) devices face significant degradation due to hot carrier injection, which affects their reliability and performance, particularly in laterally-diffused (LD) HVMOS devices, leading to increased on-resistance and reduced drain current over time.
Innovation Solution
The implementation of a high-voltage metal-oxide-semiconductor (HVMOS) device design featuring a thick gate dielectric layer in the drift region, with a thin gate dielectric layer in the channel region, reduces peak electric fields and hot carrier injection by increasing the gate oxide thickness, thereby enhancing breakdown voltage and reducing hot carrier degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a thin gate dielectric layer is used in the drift region, then device area is reduced and manufacturing is simplified, but hot carrier injection degradation increases significantly
Solution Approach 1:
The patent applies different gate dielectric thicknesses to different regions of the device: a thin gate dielectric layer in the channel region for high-speed operation and a thick gate dielectric layer in the drift region for hot carrier injection reduction. This local differentiation allows each region to be optimized for its specific function without compromising overall device performance.
Solution Approach 2:
The gate dielectric layer is segmented into two distinct thickness regions along the lateral direction: a first thickness in the channel region and a second greater thickness in the drift region. This segmentation enables independent optimization of each region's electrical characteristics, particularly reducing hot carrier effects in the drift region while maintaining channel performance.
2Reliability
If doping concentration in the drift region is increased to reduce on-resistance, then on-resistance decreases, but breakdown voltage decreases and hot carrier injection increases
Solution Approach 1:
The thick gate dielectric is applied locally to the drift region where hot carrier injection occurs, allowing high doping concentrations to be used in this region to reduce on-resistance without increasing hot carrier effects, since the thick dielectric protects against carrier injection into the gate.
Solution Approach 2:
The patent converts the potentially harmful effect of high electric fields in the drift region into a benefit by using the thick gate dielectric to contain and control the electric field, preventing hot carrier generation while allowing high doping concentrations that reduce on-resistance.
3Reliability
If gate oxide thickness is increased to reduce hot carrier injection, then hot carrier degradation is reduced, but device area and manufacturing complexity increase
Solution Approach 1:
The thick gate dielectric is applied only to the drift region where hot carrier injection is the primary concern, while the channel region maintains a thin gate dielectric for optimal switching performance. This localized approach reduces the overall area impact compared to a uniformly thick gate dielectric structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design significantly reduces hot carrier degradation, as evidenced by lower Idlin/Rdson degradation, and allows for increased doping concentration in the drift region to achieve lower on-resistance without compromising breakdown voltage, thereby improving the reliability and performance of HVMOS devices.
Implementation Method 1
reduces peak electric fields and hot carrier injection by increasing the gate oxide thickness
Implementation Method 2
reduces peak electric fields and hot carrier injection
Data Source
AI summary
In a general aspect, a high-voltage metal-oxide-semiconductor (HVMOS) device can include comprising a first gate dielectric layer disposed on a channel region of the HVMOS device and a second gate dielectric layer disposed on at least a portion of a drift region of the HVMOS device. The drift region can be disposed laterally adjacent to the channel region. The second gate dielectric layer can have a thickness that is greater than a thickness of the first gate dielectric layer.