Hardware Queue System On-Device Fault Detection
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Solution Overview
Problem
Post-silicon testing of hardware queue systems faces challenges such as high silicon space and power consumption, verification difficulties due to multi-pass consistency checking, and the need for sophisticated mechanisms to verify correct information flow, which often miss corner cases and require additional hardware, making it inefficient for scaling to full system on chip (SoC) testing.
Innovation Solution
A processor-based system that divides hardware queue systems into different types of queues, generates tests using these queues, executes multiple instances of the tests, and compares results to detect hardware faults, enabling on-device testing without external communication, and allowing for correct-by-construction tests that cover various scenarios without additional hardware or golden models.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional post-silicon testing methods with sophisticated verification mechanisms are used, then hardware faults can be detected, but silicon space and power consumption increase significantly
Solution Approach 1:
The hardware queue system performs self-testing by executing test instances internally and comparing results to detect faults. The system divides queues into types, generates test cases, executes multiple instances, and compares results without requiring external verification hardware, enabling the system to verify its own correctness while reducing power consumption and silicon space requirements
Solution Approach 2:
The patent extracts the verification function from external hardware models and golden models, moving it entirely into the hardware queue system itself. By removing the need for external verification infrastructure, the solution eliminates the associated power consumption and silicon space overhead while maintaining fault detection capability
2Reliability
If traditional post-silicon testing with external verification models is used, then testing can be performed, but additional hardware and external communication are required
Solution Approach 1:
The hardware queue system performs self-testing by executing test instances internally and comparing results to detect faults. The system divides queues into types, generates test cases, executes multiple instances, and compares results without requiring external verification hardware, enabling the system to verify its own correctness while reducing power consumption and silicon space requirements
Solution Approach 2:
The test generation and execution mechanism is designed to be universally applicable to different queue types (FIFO, LIFO, priority queues). The same test framework can verify multiple queue implementations without requiring type-specific external verification models, reducing overall device complexity while maintaining comprehensive verification coverage
3Measurement precision
If multi-pass consistency checking is used for verification, then correct information flow can be checked, but corner cases are missed and additional hardware is required
Solution Approach 1:
The patent employs dynamic test instance generation that adapts to different queue types and operational scenarios. Instead of static multi-pass checking, the system generates multiple dynamic test instances that can cover corner cases by varying test parameters and queue configurations, improving both verification precision and adaptability simultaneously
Solution Approach 2:
The verification process is segmented into distinct queue type categories (FIFO, LIFO, priority queues), with specialized test instances generated for each type. This segmentation allows the system to apply appropriate verification strategies for each queue type while maintaining comprehensive corner case coverage across all queue implementations
4Adaptability or versatility
If scaling to full system on chip testing is attempted with traditional methods, then comprehensive coverage is achieved, but efficiency decreases due to high resource requirements
Solution Approach 1:
The hardware queue system performs self-testing by executing test instances internally and comparing results to detect faults. The system divides queues into types, generates test cases, executes multiple instances, and compares results without requiring external verification hardware, enabling the system to verify its own correctness while reducing power consumption and silicon space requirements
Solution Approach 2:
The verification process is segmented into distinct queue type categories (FIFO, LIFO, priority queues), with specialized test instances generated for each type. This segmentation allows the system to apply appropriate verification strategies for each queue type while maintaining comprehensive corner case coverage across all queue implementations
Data Source
AI summary
An example system includes a processor that can receive a queue testing package. The processor can divide a hardware (HW) queue system to be tested into different types of queues. The processor can also generate a test using the different types of queues. The processor can further execute multiple instances of the generated test. The processor can also further compare results of the multiple instances of the test to detect a hardware fault in the hardware queue system.