Hybrid BGA Package with Substrate Raiser for High-Speed Interconnects
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Solution Overview
Problem
Conventional semiconductor packaging faces challenges with signal integrity due to increased electrical insertion losses and impedance discontinuities in high-speed applications, particularly in the package-to-printed circuit board vertical interconnects, which are not effectively addressed by existing methods that often compromise on reliability and current carrying capacity.
Innovation Solution
The use of a substrate raiser with varying height solder balls and conductive vias forms a hybrid BGA semiconductor package, where mini solder balls carry high-speed signals and large solder balls carry lower frequency signals or power, reducing impedance discontinuities and insertion losses through improved impedance matching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional BGA packaging is used for high-speed interconnects, then mechanical support and electrical connection are provided, but signal integrity degrades due to increased electrical insertion losses and impedance discontinuities
Solution Approach 1:
The patent applies local quality by differentiating the functionality of solder balls based on their position and electrical characteristics. High-speed signal balls are positioned in specific regions with optimized impedance characteristics, while other balls handle power or lower-speed signals. This localized optimization of solder ball function reduces impedance discontinuities and insertion losses for high-speed paths while maintaining overall package performance.
Solution Approach 2:
The patent introduces a substrate raiser structure that adds vertical dimensionality to the package architecture. This raiser creates a stepped configuration where high-speed signal paths can be routed through elevated regions with optimized impedance control. By utilizing the vertical dimension, the patent achieves better signal integrity without increasing the planar footprint, effectively addressing insertion loss issues through three-dimensional structural optimization.
2Reliability
If PTH dimensions are reduced to address over-capacitive structures, then impedance matching improves, but manufacturing complexity and reliability risks increase
Solution Approach 1:
The patent employs parameter changes by optimizing the impedance characteristics of the substrate raiser and associated via structures. By carefully controlling the dimensions, materials, and geometries of the raiser and vias, the patent achieves target impedance values for high-speed signals without requiring excessive reduction of PTH dimensions. This parameter optimization balances impedance matching requirements with manufacturing feasibility, avoiding the reliability risks associated with overly aggressive via size reduction.
3Reliability
If anti-pad geometry is enlarged to reduce PTH capacitance, then impedance matching improves, but routing-over-void phenomena occur causing signal distortion
Solution Approach 1:
The patent applies segmentation by dividing the substrate into distinct functional regions: elevated raiser regions for high-speed signals and lower regions for other functions. This segmentation allows high-speed signal paths to be routed through controlled-impedance pathways in the raiser structure, avoiding the need for large anti-pad geometries that would create routing-over-void issues. The segmented architecture isolates high-speed signals from problematic via structures while maintaining effective impedance control.
4Reliability
If BGA dimension is reduced to reduce capacitance, then impedance matching improves, but current carrying capacity decreases
Solution Approach 1:
The patent applies local quality by assigning different current-carrying requirements to different regions of the BGA array. High-speed signal balls with lower current requirements are positioned in the substrate raiser region where smaller dimensions achieve adequate impedance control. Power delivery balls with higher current requirements are positioned in regions with larger dimensions and direct substrate connection. This localized differentiation allows the package to achieve both good impedance matching for high-speed signals and adequate current carrying capacity for power delivery without compromising either function.
Data Source
AI summary
According to various examples, a semiconductor package is described including a substrate raiser with interconnect vias that may be positioned on the bottom side of a substrate and mini solder balls positioned on the interconnect vias and a plurality of large solder balls positioned on the bottom side of the substrate adjacent to the substrate raiser, wherein the mini solder balls and the large solder balls extend approximately a same height from the substrate for mounting on a printed circuit board.