Hybrid-Bonded Die Structure With CTE Buffer for Delamination Control
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Solution Overview
Problem
The semiconductor industry faces challenges in integrating smaller electronic components due to stress and reliability issues arising from coefficient of thermal expansion (CTE) mismatches between encapsulants and integrated circuit dies, leading to delamination of dielectric layers.
Innovation Solution
Incorporation of stress reduction compounds, such as polymer materials with silica fillers, as buffer layers around integrated circuit dies to mitigate stress at bonding interfaces, combined with hybrid bonding techniques to enhance adhesion and reduce delamination risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If encapsulants are used to protect integrated circuit dies, then reliability is improved, but stress at bonding interfaces increases due to CTE mismatch
Solution Approach 1:
A buffer layer comprising a stress reduction compound is introduced between the encapsulant and the integrated circuit die. This intermediary layer has a coefficient of thermal expansion that is greater than the semiconductor material but less than the encapsulant, thereby mediating the stress caused by CTE mismatch and protecting the bonding interface from delamination
Solution Approach 2:
The buffer layer is formed using a composite material consisting of a polymer matrix combined with inorganic fillers (such as silica, alumina, or titania). This composite structure allows tuning of the CTE to an intermediate value between the die and encapsulant, while also providing mechanical stress reduction properties
2Productivity
If minimum feature size is reduced to increase integration density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent modifies material parameters (composition, CTE, mechanical properties) of the buffer layer to optimize its stress reduction capability. By changing the polymer matrix composition and filler content, the material properties are tuned to provide maximum stress relief while maintaining compatibility with miniaturized die structures
3Reliability
If buffer layers are added to reduce stress, then reliability is improved, but device complexity increases
Solution Approach 1:
The buffer layer is applied selectively around specific regions of the integrated circuit die, particularly at the bonding interfaces where stress concentration occurs. This localized approach provides stress relief where needed most while minimizing the overall structural complexity and material usage
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves yield and reliability of die structures by reducing stress at bonding interfaces, thereby enhancing the integration density and performance of semiconductor devices.
Implementation Method 1
stress and reliability issues arising from coefficient of thermal expansion (CTE) mismatches between encapsulants and integrated circuit dies
Implementation Method 2
hybrid bonding techniques to enhance adhesion and reduce delamination risks
Data Source
AI summary
Various embodiments include die structures and methods of forming die structures. In an embodiment, a device includes: a lower substrate; upper integrated circuit dies bonded to the lower substrate with dielectric-to-dielectric bonds and with metal-to-metal bonds, the upper integrated circuit dies including a semiconductor material; a buffer layer around the upper integrated circuit dies, the buffer layer including a stress reduction compound, a coefficient of thermal expansion of the stress reduction compound being greater than a coefficient of thermal expansion of the semiconductor material; and an encapsulant around the buffer layer and the upper integrated circuit dies, the encapsulant including a molding compound, a coefficient of thermal expansion of the molding compound being greater than the coefficient of thermal expansion of the stress reduction compound.