Hybrid Bonded 3D IC Package for High Density I/O
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Solution Overview
Problem
As semiconductor technologies advance, the increasing density of input/output (I/O) pads on integrated circuit dies complicates die packaging, and there is a need for greater parallel processing capabilities, which existing packaging technologies struggle to address effectively.
Innovation Solution
The solution involves forming an integrated circuit package by stacking memory devices on a processor device without integrated memories, using hybrid bonding to connect them, allowing for shorter interconnects and improved performance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If integrated circuit dies are singulated from wafers before packaging, then fan-out packages can be formed to redistribute I/O pads to greater area, but the area available for I/O pads decreases while I/O pad density increases
Solution Approach 1:
The patent transitions from planar I/O pad arrangement to three-dimensional stacked architecture, where memory devices are vertically stacked on the processor device. This dimensional change allows I/O pads to be redistributed across multiple layers and a larger overall area, resolving the contradiction between limited planar area and increasing I/O pad density requirements
Solution Approach 2:
The patent implements nested stacking where memory devices are placed on top of the processor device, creating a hierarchical structure. This nesting approach allows multiple I/O pads to be accommodated within the vertical stack, effectively increasing the functional I/O area without expanding the processor device footprint
2Productivity
If multiple dies are integrated through packaging technologies, then greater parallel processing capabilities are achieved, but interconnect length increases causing higher latency and power consumption
Solution Approach 1:
The patent merges the processor device and memory devices into a single integrated stack structure. This combination eliminates the need for long external interconnects between separate packages, as memory and processor are directly coupled through short vertical interconnects, thereby reducing latency while maintaining high parallel processing capability
Solution Approach 2:
The patent moves from horizontal integration of multiple dies in separate packages to vertical integration in a stacked configuration. This dimensional transition dramatically shortens interconnect lengths by placing memory directly above the processor, reducing both latency and power consumption while preserving parallel processing throughput
3Productivity
If multiple dies are integrated through packaging technologies, then greater parallel processing capabilities are achieved, but interconnect length increases causing higher power consumption
Solution Approach 1:
The patent combines processor and memory into a unified stacked structure, eliminating long inter-package interconnects that consume significant power. The direct vertical coupling reduces energy loss in signal transmission while maintaining high parallel processing performance
Solution Approach 2:
The vertical stacking architecture replaces horizontal die-to-die interconnections with vertical interconnects through the stack. This dimensional change dramatically reduces interconnect length and associated power consumption, as electrical signals travel much shorter distances between processor and memory
Data Source
AI summary
In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.