Hybrid Bonding Structure With Intermediate-CTE Buffer Layer

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Solution Overview

Problem

In 3D IC hybrid bonding, the difference in thermal expansion coefficients between metal and dielectric materials leads to thermal stress and cracking during the bonding process.

Innovation Solution

A buffer structure with a coefficient of thermal expansion ranging between that of the metal and dielectric materials is introduced to separate the conductive and dielectric structures, mitigating thermal stress and preventing cracking.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If hybrid bonding is used to connect dies with small copper-to-copper connections, then interconnect density is improved, but thermal stress and cracking occur due to different coefficients of thermal expansion between metal and dielectric materials

Engineering Contradiction:
Improveinterconnect densityVSAvoidcrack resistance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A buffer layer is introduced as an intermediary between the metal interconnect and the dielectric material. This buffer layer has a coefficient of thermal expansion that is intermediate between those of the metal and dielectric, serving as a mediator that gradually transitions the thermal expansion properties and prevents direct stress concentration at the metal-dielectric interface, thereby preventing cracking while maintaining high interconnect density

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The coefficient of thermal expansion parameter is changed by introducing a buffer layer with intermediate CTE properties. Instead of having a abrupt transition between metal and dielectric CTE values, the buffer layer creates a gradual parameter transition, reducing thermal stress and preventing cracks during thermal cycling while preserving the hybrid bonding structure's high density benefits

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If metal and dielectric materials are used in hybrid bonding, then bonding functionality is achieved, but cracks are induced during the bonding process due to CTE mismatch

Engineering Contradiction:
Improvebonding functionalityVSAvoidstructural integrity
Core Design Contradiction:
Adaptability or versatilityVSStrength

Solution Approach 1:

The buffer layer acts as a mediator between the metal bonding pad and the dielectric structure, providing a transition zone that accommodates the CTE mismatch. This intermediary layer prevents direct stress transmission from the metal to the dielectric during thermal expansion and contraction, maintaining structural integrity while preserving the hybrid bonding functionality

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The hybrid bonding structure is enhanced by creating a composite material system that includes metal, buffer layer, and dielectric components. This composite structure leverages the complementary properties of each material layer, where the buffer layer's intermediate CTE properties bridge the gap between metal and dielectric, ensuring both bonding functionality and crack resistance

Inventive Principle:
Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The buffer structure effectively tolerates the thermal expansion differences, preventing cracks during hybrid bonding and ensuring the integrity of the semiconductor device structure.

Implementation Method 1

A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure

Methodology Applied
Scientific EffectThermal expansion: Thermal Expansion

Data Source

PatentUS20240153902A1Semiconductor device structure including a bonding structure
Publication Date: 2024.05.09 NAN YA TECH
  • US20240153902A1 patent drawing
  • US20240153902A1 patent drawing
  • US20240153902A1 patent drawing

AI summary

A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.