Hybrid Bump Structure with Accommodating Space for Solder Overflow Control

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

In miniaturized electronic products, the close spacing between bumps and connection pads leads to solder overflow during reflow, causing short circuits and reducing product yield in conventional semiconductor packaging methods.

Innovation Solution

A semiconductor manufacturing method involving a carrier with a metallic layer and photoresist layers to form hybrid bumps with a base, projecting, and accommodating spaces, where the second connection layers fill the accommodating spaces, preventing overflow and ensuring reliable connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the spacing between bumps and connection pads is miniaturized to accommodate smaller electronic products, then the volume and scale of electronic products are reduced, but solder overflow to adjacent bumps or connection pads occurs during reflow, causing short circuits and lowering product yield rate

Engineering Contradiction:

Improvevolume of electronic productsVSAvoidproduct yield rate

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The first connection layer is designed with non-uniform thickness, featuring a base portion, a projecting portion, and an accommodating space. This local variation in thickness creates a contour that guides solder flow into the accommodating space, preventing overflow to adjacent bumps while maintaining miniaturized dimensions.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The first connection layer with its specific contour shape is formed before the reflow process. This preliminary structuring of the connection layer creates predetermined accommodating spaces that actively guide and contain the solder during the subsequent reflow process, preventing short circuits before they can occur.

Inventive Principle:

Principle #10Preliminary action

2Ease of manufacture

If conventional soldering methods are used with miniaturized spacing, then manufacturing process simplicity is maintained, but solder overflow causes short phenomenon reducing reliability

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidpackage reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The thickness parameter of the first connection layer is varied to create different functional regions (base portion, projecting portion, accommodating space). This parameter change transforms a simple planar layer into a three-dimensional structure that actively prevents solder overflow, improving reliability without complicating the overall manufacturing process.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9059260B2Semiconductor manufacturing method and semiconductor structure thereof

Publication Date: 2015.06.16 CHIPBOND TECH

AI summary

A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.