Hybrid Non-Uniform Convolution Transform Engine for Deep Learning

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Solution Overview

Problem

Deep learning convolutional neural networks (CNNs) face resource-demanding computational workloads due to intensive convolution operations, which are not efficiently addressed by existing technologies.

Innovation Solution

A system and method that selectively enable processing elements with more adders than multipliers to perform convolution operations in either a transformed domain or directly, based on input size, utilizing the Winograd transform for efficient computations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional convolution computations are used in CNNs, then the convolution operations can be performed, but the computational workload becomes intensive and resource-demanding

Engineering Contradiction:
Improveconvolution computation efficiencyVSAvoidcomputational resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent applies parameter changes by transforming the convolution operation from the spatial domain to the frequency domain using Fast Fourier Transform (FFT). This changes the computational parameters from direct convolution (O(n²)) to frequency domain multiplication (O(n log n)), significantly reducing computational complexity and resource consumption while maintaining computation accuracy.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If more adders are provided in processing elements, then the transformed domain computation can be performed efficiently, but the device complexity increases

Engineering Contradiction:
Improvetransformed domain computation speedVSAvoidprocessing element structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent employs dynamics by making the processing elements reconfigurable. The same processing element can be dynamically configured to perform different operations (direct convolution or transformed domain convolution) based on the input characteristics. This allows the system to adapt its structure to the computational requirements, achieving high performance for transformed domain operations without permanently increasing device complexity.

Inventive Principle:
Principle #15Dynamics

3Adaptability or versatility

If the system supports both transformed domain and direct convolution modes, then adaptability to different input sizes is improved, but the device complexity increases

Engineering Contradiction:
Improveinput size compatibilityVSAvoidmulti-mode processing structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements universality by designing processing elements that can perform multiple functions. Each processing element is capable of executing both direct convolution operations and transformed domain convolution operations, eliminating the need for separate dedicated hardware for each mode. This multi-functional design achieves adaptability to different input sizes while controlling device complexity through resource sharing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10755169B2Hybrid non-uniform convolution transform engine for deep learning applications
Publication Date: 2020.08.25 MEDIATEK INC
  • US10755169B2 patent drawing
  • US10755169B2 patent drawing
  • US10755169B2 patent drawing

AI summary

A system performs convolution operations based on an analysis of the input size. The input includes data elements and filter weights. The system includes multiple processing elements. Each processing element includes multipliers and adders, with more of the adders than the multipliers. According to at least the analysis result which indicates whether the input size matches a predetermined size, the system is operative to select a first mode or a second mode. In the first mode, a greater number of the adders than the multipliers are enabled for each processing element to multiply transformed input and to perform an inverse transformation. In the second mode, an equal number of the adders and the multipliers are enabled for each processing element to multiply-and-accumulate the input. One or more of the multipliers are shared by the first mode and the second mode.