Hybrid Fanout Semiconductor Assembly Without Package Substrate
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Solution Overview
Problem
Semiconductor packages face challenges in reducing volume while maintaining strength and reliability, particularly due to the thickness of semiconductor dies and the presence of a package substrate, which complicates manufacturing and increases costs.
Innovation Solution
A hybrid fanout scheme is employed, eliminating the package substrate and integrating fanout wafer level packaging to form conductive traces and through mold vias on the semiconductor die, allowing direct attachment to a PCB without a package substrate, enhancing die strength and reducing thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If direct chip attach methods are used to reduce footprint, then the volume of semiconductor packages is reduced, but the manufacturing complexity and cost increase
Solution Approach 1:
The patent divides the semiconductor package into distinct functional layers: a substrate layer, a molding layer with embedded conductive traces, and a die layer. This segmentation allows each layer to be optimized independently, simplifying manufacturing while achieving compact volume through the integrated fanout structure that eliminates separate package substrates.
Solution Approach 2:
The patent transitions from planar 2D packaging to 3D vertical stacking by implementing through-mold vias that extend conductive paths through the molding layer. This dimensional change enables direct attachment to PCBs while maintaining reduced footprint, resolving the contradiction between compact volume and manufacturing simplicity.
2Length of stationary object
If semiconductor die thickness is reduced to stack multiple dies, then the overall height of semiconductor packages is reduced, but the mechanical strength and reliability of individual dies deteriorate
Solution Approach 1:
The patent employs a composite structure where thinned semiconductor dies are bonded to a reinforced substrate with integrated fanout traces. The substrate acts as a mechanical support that compensates for the reduced strength of thinned dies, enabling height reduction while maintaining reliability through the composite assembly rather than relying on die thickness alone.
Solution Approach 2:
The substrate with embedded conductive traces serves as an intermediary between thinned semiconductor dies and the external environment. This intermediary provides mechanical support and electrical connectivity, allowing dies to be thinned for stacking while the substrate maintains overall structural integrity and reliability.
3Ease of manufacture
If package substrate is eliminated to reduce costs and simplify design, then manufacturing cost and design complexity are reduced, but the electrical connectivity and mechanical support functions must be integrated elsewhere
Solution Approach 1:
The patent merges the electrical connectivity function and mechanical support function into the substrate with integrated fanout traces. By combining these functions into a single component rather than using separate package substrates, the design is simplified while maintaining all necessary functions, directly addressing the contradiction between ease of manufacture and integration complexity.
Data Source
AI summary
Hybrid fanouts for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, at least one edge a first semiconductor die is attached to a molding including through mold vias (TMVs). Conductive traces may be formed on a first side of the first semiconductor die, where the first side includes integrated circuitry coupled to the conductive traces. Moreover, conductive pads may be formed on a surface of the molding, which is coplanar with the first side. The conductive pads are coupled to first ends of the TMVs, where second ends of the TMVs are coupled to bond wires connected to one or more second semiconductor dies that the first semiconductor die carries. Conductive bumps can be formed on the conductive traces and pads such that the first semiconductor die and the molding attached thereto can be directly attached to a printed circuit board.