Hybrid Gate Line Driver Layout for Stable Long-Line Transmission

The gate line driving circuit is divided into multiple stages with intermediate buffering. The shift register is segmented into multiple banks, each driving a portion of the gate lines. Intermediate buffer circuits are inserted along the gate lines to refresh and retransmit signals, dividing the long transmission path into shorter segments that maintain signal integrity.

Buffer circuits and driver transistors are introduced as intermediary elements between the shift register and the gate lines. These intermediaries actively refresh and retransmit the gate signals, compensating for signal decay during long distance transmission across large-scale panels.

Different transistor types are used in different locations within the gate driving circuit. LTPS transistors with higher mobility are deployed in the pull-up transistor positions where high driving capability is critical for long gate lines, while maintaining compact layout through optimized circuit design.

The gate driving circuit employs a hybrid transistor architecture combining LTPS transistors for high-current driving functions and IGZO transistors for low-leakage control functions. This composite approach leverages the complementary strengths of different semiconductor materials to achieve both high driving capability and area efficiency.

Different transistor types are strategically placed in different circuit locations. LTPS transistors are used where high driving current is needed, while IGZO transistors with superior off-state characteristics are used in control and switching positions where leakage current must be minimized to maintain voltage stability.

The circuit architecture integrates LTPS and IGZO transistors in a complementary manner. The LTPS transistors provide the necessary driving current for long gate lines, while the IGZO transistors control leakage current in the control circuitry, together achieving both high driving capability and voltage stability.