Hybrid High-k Replacement Gate Stack for PMOS Work Function Stability
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Solution Overview
Problem
The challenge in integrated circuits is to address the issue of PMOS metal gate work function changes at high temperatures, which affects transistor performance, and to improve the quality of gate dielectrics to reduce short channel effects and enhance carrier mobility.
Innovation Solution
The solution involves forming a metal gate NMOS transistor with a high-k first gate dielectric on a high-quality thermally grown interface dielectric and a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric, allowing for independent optimization of dielectrics for each type of transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thin silicon dioxide dielectric is grown chemically using SC1 to enable metal gate deposition at limited temperatures, then the metal gate can be formed, but the quality of the silicon dioxide dielectric is marginal
Solution Approach 1:
The gate dielectric structure is segmented into multiple layers: a first high-k dielectric layer deposited on the silicon surface, a second high-k dielectric layer deposited over the first layer, and an interface dielectric layer between the silicon and first high-k layer. This segmentation allows each layer to be optimized independently for its specific function.
Solution Approach 2:
Different dielectric materials are used at different locations within the gate stack. The interface dielectric layer (thermally grown silicon dioxide) provides high quality at the silicon interface, while the high-k dielectric layers (such as hafnium oxide) provide high capacitance further from the interface. Each layer is tailored to its local requirements.
2Ease of manufacture
If polysilicon gates are used with silicon dioxide gate dielectric, then the transistors can be built in the usual manner, but the polysilicon work function changes at high temperatures affecting PMOS performance
Solution Approach 1:
The gate dielectric structure is changed from conventional silicon dioxide to a multi-layer high-k dielectric structure. This parameter change allows the use of metal gates with stable work functions that do not change at high temperatures, while maintaining compatibility with standard fabrication processes through the interface dielectric layer.
3Device complexity
If the same gate dielectric structure is used for both NMOS and PMOS transistors, then the process is simplified, but the dielectric quality cannot be independently optimized for each transistor type
Solution Approach 1:
The gate dielectric structure is customized for each transistor type: NMOS transistors receive a first gate dielectric structure optimized for their requirements, while PMOS transistors receive a second gate dielectric structure optimized for their requirements. This allows independent optimization of dielectric quality, thickness, and material composition for each transistor type while maintaining a unified process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the quality of gate dielectrics, enhances carrier mobility, reduces gate current, and prolongs battery life by effectively managing the work function changes and optimizing the dielectric layers for both NMOS and PMOS transistors.
Implementation Method 1
a high-k first gate dielectric on a high quality thermally grown interface dielectric
Implementation Method 2
a high-k last gate dielectric on a chemically grown interface dielectric
Data Source
Figure 1A~1B
Figure 1C~1D
Figure 1E
AI summary
An integrated circuit is provided with a metal gate NMOS transistor (130) with a high-k first gate dielectric (108) on a high quality thermally grown interface dielectric (106) and with a metal gate PMOS transistor (132) with a high-k last gate dielectric (136) on a chemically grown interface dielectric (134). Process flows are provided for forming an integrated circuit with a metal gate NMOS transistor (130) with a high-k first gate dielectric (108) on a high quality thermally grown interface dielectric (106) and with a metal gate PMOS transistor (132) with a high-k last gate dielectric (136) on a chemically grown interface dielectric (134).