Hybrid IC Metal Layer for Wordline Capacitance and Bitline Resistance
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Solution Overview
Problem
Current BEOL technologies face challenges in fabricating metal layers that meet the conflicting requirements of low capacitance for wordlines and low resistance for bitlines in memory circuits, as the height of metal layers cannot be optimized for both due to resistance changes with critical dimensions, and using two different metals complicates polishing processes.
Innovation Solution
The introduction of hybrid metal layers with different structures, where one metal (ruthenium) has lower resistance for narrower widths and another metal (copper) with lower capacitance for wider structures, enclosed by a conductive barrier to prevent contamination, using double-deck patterning to achieve varying heights and optimize resistance and capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the height of metal layer is reduced, then capacitance is reduced for wordlines, but resistance increases
Solution Approach 1:
The patent applies local quality by creating different metal layer heights in different regions of the same metal layer. Specifically, wordline regions have reduced height to minimize capacitance, while bitline regions maintain full height to ensure low resistance. This is achieved through selective etching processes that remove metal from specific areas while preserving it in others, allowing each region to be optimized for its specific function.
2Reliability
If two different metals are used to form metal layer, then resistance and capacitance requirements can be met, but polishing process becomes complicated
Solution Approach 1:
The patent segments the metal layer into multiple sub-layers with different heights and materials. The first metal layer contains ruthenium structures for wordlines with reduced height, while the second metal layer contains copper structures for bitlines with full height. This segmentation allows each metal to be optimized for its specific application while maintaining a unified overall structure that can be processed together through single polishing steps.
Solution Approach 2:
The patent employs composite materials by combining ruthenium and copper in a hybrid metal layer structure. Ruthenium is used in regions requiring low capacitance (wordlines) while copper is used in regions requiring low resistance (bitlines). The composite structure is integrated through a unified fabrication process that includes selective deposition and etching, followed by a single polishing step that handles both materials appropriately.
3Manufacturing precision
If metal critical dimension becomes tighter, then resistance changes, but optimal resistance cannot be met by one common metal material
Solution Approach 1:
The patent applies parameter changes by varying both the material composition and physical dimensions (height) of metal structures based on their specific function. Ruthenium structures for wordlines have reduced height parameters to minimize capacitance, while copper structures for bitlines maintain full height parameters to ensure low resistance. This allows optimal electrical characteristics to be achieved for each metal type according to its specific application requirements.
Data Source
AI summary
An IC device includes a transistor, a first layer, and a second layer. The first layer is coupled to the transistors and is between the transistor and the second layer in a first direction. The first layer includes a first structure and a second structure. The first structure includes a first metal (e.g., Ru). The second structure includes a second metal (e.g., Cu). The second structure may be wrapped around by a different material that may include a third metal (e.g., Co). The first structure may be shorter than the second structure in the first direction and narrower than the second structure in a second direction orthogonal to the first direction. The first structure may be closer to the second layer than the second structure in the first direction. The first structure may be a wordline of a memory. The second structure may be a bitline.


