Hybrid-Layer Type-3 PCB Layout for Shorter Via Stubs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed signals in Type-3 printed circuit boards (PCBs) experience signal integrity degradation due to signal reflections caused by via stubs, which are exacerbated by the discrepancy in via lengths and layer thicknesses, particularly in core areas.
Innovation Solution
The PCB design incorporates a core area with additional layers and shorter PTH vias, achieved through a sequential lamination process of sub-boards, allowing for reduced stub portions and a lower z-height in non-core areas, enabling efficient signal routing and component placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Type-3 PCB with uniform layer count is used throughout, then manufacturing is simpler and cost-effective, but signal integrity degrades due to long via stubs in the core area
Solution Approach 1:
The patent applies local quality by creating a hybrid layer count PCB where the core area has a different layer configuration (higher layer count) compared to the edge areas (lower layer count). This allows the core area to have shorter via stubs for better signal integrity while keeping the edge areas simpler. The selective placement of signal layers and ground layers in specific regions optimizes signal performance where needed without complicating the entire PCB structure.
Solution Approach 2:
The PCB is segmented into different functional zones: a core area with higher layer count for high-speed signals and a edge area with lower layer count for I/O connections. This segmentation allows each zone to be optimized independently - the core area uses more layers to reduce via stub length for signal integrity, while edge areas use fewer layers to maintain manufacturing simplicity and cost-effectiveness.
2Reliability
If additional layers are added to the core area to reduce via stub length, then signal reflections are reduced, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is segmented into stages: first, a base PCB structure is manufactured with standard layering; then, additional core area layers are selectively added only where needed for high-speed signal routing. This segmentation allows the majority of the PCB to be manufactured using standard, cost-effective processes while only specific regions receive the enhanced layer structure required for signal integrity.
Solution Approach 2:
The enhanced layer structure with additional signal and ground layers is applied locally only to the core area where high-speed signals require shorter via stubs. The edge areas maintain the standard, simpler layer configuration. This localized enhancement minimizes the impact on manufacturing complexity while providing signal integrity benefits precisely where needed.
3Reliability
If via stub length is reduced in the core area, then signal reflections are minimized, but PCB z-height increases
Solution Approach 1:
The increased z-height is localized only to the core area where additional layers are stacked to reduce via stub length. The edge areas maintain the original, lower z-height profile. This localized height variation allows the core area to achieve better signal integrity through shorter stubs without significantly impacting the overall PCB form factor or component clearance requirements.
Data Source
AI summary
In one embodiment, a printed circuit board includes a first circuit board portion comprising a set of first conducting layers and one or more plated through hole (PTH) vias formed through the first conducting layers and a second circuit board portion comprising a set of second conducting layers. The second circuit board portion has an area less than an area of the first circuit board portion, and the second circuit board portion is coupled to the first circuit board portion via a laminate layer such that the first and second conducting layers are parallel with one another. The printed circuit board further includes one or more PTH vias formed through the first and second conducting layers in an area of the printed circuit board where the first and second circuit board portions overlap.