Hybrid MAC Array for Convolution and Vector Operation Reuse
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing neural network hardware architectures are inefficient for parallel processing of convolution and vector operations, requiring separate hardware for each type of operation, which increases cost and design complexity.
Innovation Solution
A hybrid PE array that reuses MAC resources for both convolution and vector operations, switching between modes through control signals to perform summations or comparisons, allowing parallel execution of both types of computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate hardware processors are used for convolution and vector operations, then each operation type can be processed with dedicated optimization, but hardware cost and design complexity increase
Solution Approach 1:
The patent implements a universal processing element that can perform both convolution operations and vector operations by configuring the same hardware resources (MAC circuits, weight buffers, activation buffers) with different operational parameters. The processing element receives control signals that determine whether to execute convolution or vector operations, eliminating the need for separate dedicated hardware for each operation type while maintaining processing efficiency
Solution Approach 2:
The patent merges convolution processing and vector operation processing into a single integrated hardware architecture. The MAC circuits, weight buffers, and activation buffers are shared resources that can be dynamically allocated to either convolution or vector operations based on the computational task, reducing overall hardware requirements while maintaining both functionality
2Adaptability or versatility
If SIMD vector processors are used for vector operations, then vector processing capability is provided, but parallel processing efficiency for multiple vectors deteriorates
Solution Approach 1:
The patent divides the processing architecture into multiple independent processing elements that can operate in parallel. Each processing element can handle vector operations independently, and multiple processing elements can simultaneously process multiple vectors, achieving true parallel processing efficiency while maintaining vector processing capability
3Productivity
If dedicated hardware is installed for vector operations, then vector operation performance is improved, but hardware cost increases
Solution Approach 1:
The patent makes the same hardware resources (MAC circuits, buffers, controllers) universal by enabling them to perform both convolution operations and vector operations. The processing element is configured through control signals to execute the appropriate operation type, eliminating the need for additional dedicated hardware for vector operations while maintaining high performance for both operation types
Data Source
AI summary
This application describes hybrid hardware accelerators, systems, and apparatus for performing various computations in neural network applications using the same set of hardware resources. An example accelerator may include weight selectors, activation input interfaces, and a plurality of Multiplier-Accumulation (MAC) circuits organized as a plurality of MAC lanes Each of the plurality of MAC lanes may be configured to: receive a control signal indicating whether to perform convolution or vector operations; receive one or more weights according to the control signal; receive one or more activations according to the control signal; and generate output data based on the one or more weights and the one or more input activations according to the control signal and feed the output data into an output buffer. Each of the plurality of MAC lanes includes a plurality of multiplier circuits and a plurality of adder-subtractor circuits.