Hybrid Matrix Multiplier With Analog Charge Accumulation
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Solution Overview
Problem
Existing computing systems face challenges in performing matrix multiplication efficiently and with low power consumption, particularly for large matrices and high data rates, which is crucial for real-time processing in safety-critical and portable device applications.
Innovation Solution
The development of hybrid computing hardware accelerators that utilize digital binary single-bit multipliers with analog accumulators, where the multiplication results are stored as charges in capacitors, allowing for nearly instantaneous summation without external power, forming a high-speed and low-power multiply-accumulate circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital binary multipliers and adders are used for matrix multiplication, then computation can be performed, but processing speed is insufficient for real-time applications
Solution Approach 1:
The patent replaces digital binary adders with analog accumulators that perform summation through physical charge accumulation. The analog domain naturally performs addition by summing charge values from multiple capacitors, eliminating the need for sequential digital addition operations. This substitution of mechanical/digital addition with physical analog accumulation dramatically increases computation speed for real-time matrix multiplication applications.
Solution Approach 2:
The patent changes the operational parameter from digital binary states to analog charge values. By representing data and intermediate results as continuous charge values in capacitors rather than discrete binary numbers, the system enables parallel analog computation. This parameter change allows simultaneous multiplication and accumulation operations to occur at high speed, improving both processing speed and computation rate.
2Productivity
If accelerated computing hardware is used for large matrices, then computation rate increases, but power consumption increases
Solution Approach 1:
The patent substitutes power-hungry digital adder circuits with passive analog accumulators. The analog accumulation process relies on natural charge flow and capacitor storage rather than active digital logic gates, significantly reducing power consumption. The bit-multiply circuits use minimal power to generate charge values that are passively accumulated, enabling high computation rates with low power consumption suitable for portable devices.
Solution Approach 2:
The analog accumulators perform the addition function autonomously through physical charge accumulation without requiring external power during the accumulation phase. The capacitors naturally sum the charge values from multiple bit-multiply circuits through parallel charge flow, eliminating the need for powered adder circuits. This self-service mechanism reduces overall system power consumption while maintaining high computation rates.
3Ease of manufacture
If digital binary multipliers are used, then multiplication can be performed, but the system lacks low-power accumulation capability
Solution Approach 1:
The patent merges the multiplication and accumulation functions into a unified hybrid circuit architecture. The bit-multiply circuits generate charge values that are directly accumulated by shared capacitors, combining what would traditionally be separate multiply and add operations. This merging eliminates the need for separate powered adder circuits, reducing power consumption while maintaining ease of manufacture through a streamlined hybrid design that leverages both digital and analog strengths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables fast, efficient, and low-power matrix multiplication, reducing power consumption and increasing processing speed, making it suitable for real-time applications in safety-critical and portable devices.
Implementation Method 1
a bit-multiply circuit for multiplying the first single-bit value times the second single-bit value to calculate a product, and an analog storage circuit, wherein the bit-multiply circuit is operable to deposit a charge in the analog storage circuit representative of the product
Implementation Method 2
The analog storage circuit can be a capacitor
Implementation Method 3
By combining capacitor charges, the summation operation is nearly instantaneous, relying on the rate at which charges in a conductor can flow
Data Source
AI summary
A hybrid multiply-accumulate circuit includes an array of single-bit multiply-accumulate circuits. Each single-bit multiply accumulate circuit has a first storage element for storing a first single-bit value, a second storage element for storing a second single-bit value, a multiply circuit for multiplying the first single-bit value times the second single-bit value to calculate a product, and an analog storage circuit. The multiply circuit is operable to deposit a charge in the analog storage circuit representative of the product. The analog storage circuits are together operable to combine the charges deposited in each analog storage circuit to provide an accumulated charge representative of a sum of the products. A hybrid matrix multiplier includes an array of hybrid multiply-accumulate circuits and an adder operable to add the accumulated values to produce a matrix value. The matrix value and the adder can be digital or analog.