Hybrid Volatile Non-Volatile Memory Array Design
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Solution Overview
Problem
Existing non-volatile memory arrays face challenges with high access times and surface area usage due to the slow read and write operations of resistive elements, which are exacerbated by the need for additional circuits for programming and reading.
Innovation Solution
A memory array design incorporating both volatile and non-volatile memory cells, where a shared read/write circuit efficiently reads and writes data between volatile SRAM cells and current-programmable resistive elements, reducing the number of transistors and sense amplifiers required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If additional circuits are included within each memory cell to program and read resistive elements, then access times are improved, but area usage and power consumption increase
Solution Approach 1:
The patent merges volatile and non-volatile memory cells into a unified memory structure where both cell types share common bit lines and read/write circuits. This consolidation eliminates the need for separate programming and reading circuits for each cell type, reducing the area per memory cell while maintaining fast access times through the volatile portion.
Solution Approach 2:
The read/write circuit is designed to universally handle both volatile and non-volatile memory cells through the same bit lines and control logic. This multi-functional approach allows a single circuit design to serve multiple purposes, reducing overall circuit complexity and area usage compared to having dedicated circuits for each memory type.
2Duration of action of stationary object
If resistive elements are used for non-volatile storage, then data retention is improved, but read and write operation speeds deteriorate
Solution Approach 1:
The memory cell is segmented into two distinct portions: a volatile memory cell for fast read/write operations and a non-volatile memory cell for data retention. Each portion can be independently accessed or operated, allowing the system to leverage the speed of volatile memory while maintaining the data retention capabilities of non-volatile memory.
Solution Approach 2:
The volatile memory cell acts as an intermediary between the fast read/write circuits and the slower non-volatile memory cell. Data can be quickly written to or read from the volatile portion, which then interfaces with the non-volatile portion for persistent storage, effectively mediating between speed and retention requirements.
3Measurement precision
If sense amplifiers are added to read resistive states, then reading accuracy is improved, but device complexity increases
Solution Approach 1:
The read circuit for the non-volatile memory cell is merged with the existing read circuit for the volatile memory cell, sharing common bit lines, comparators, and control logic. This consolidation reduces the number of separate sense amplifiers needed while maintaining reading accuracy through the shared high-precision read path.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves faster access times and reduced area usage while maintaining non-volatile data storage, as the shared circuitry minimizes transistor count and eliminates the need for large sense amplifiers, thereby improving performance and efficiency.
Implementation Method 1
An example of such a current-programmable resistive element is a spin-transfer torque (STT) element, which is based on magnetic tunnel junctions (MTJs).
Data Source
Figure 1~3
Figure 4~5F
Figure 6~7A
AI summary
The invention relates to a memory array comprising: a plurality of volatile memory cells (202), each including a latch (206, 208); and a plurality of non-volatile memory cells (204), each including at least one resistive element (218) that can be programmed by the direction of a current passed therethrough in order to take at least two resistive states (Rmin' Rmax), each of the non-volatile memory cells being associated with a corresponding cell from the volatile memory cells.