Hybrid Memory Decoder Circuit for Low-Leakage Line Biasing
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Solution Overview
Problem
As memory cell size scales down, decoder circuits face challenges in supporting corresponding operating voltages, leading to performance degradation such as increased power consumption and current leakage, which limits the scaling of memory devices.
Innovation Solution
Incorporating a hybrid decoder circuit with a planar transistor and a trench transistor, where the trench transistor's gate electrode extends into a cavity, reducing its length and asymmetrical spacers to minimize leakage current and improve biasing accuracy, allowing the decoder circuit to scale with memory cell size while maintaining operating voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If decoder circuits are scaled down with memory cell size, then memory device area is reduced, but power consumption increases and current leakage worsens
Solution Approach 1:
The patent transitions from planar transistors to three-dimensional trench transistors, where the gate electrode extends vertically into a cavity formed in the substrate. This vertical dimension allows the gate to better control the channel while occupying less lateral area, enabling area reduction without proportionally increasing leakage current.
Solution Approach 2:
The patent modifies the transistor structure parameters by creating a trench cavity in the substrate and forming the gate electrode within this cavity. This structural parameter change increases the gate-to-channel control efficiency and reduces the off-state leakage current, allowing the decoder circuit to be scaled down while maintaining acceptable power characteristics.
2Area of stationary object
If decoder circuits are scaled down with memory cell size, then memory device area is reduced, but biasing accuracy deteriorates
Solution Approach 1:
By moving to three-dimensional trench transistors with vertical gate electrodes extending into substrate cavities, the patent achieves better electrostatic control over the channel. This enhanced control allows for more precise biasing of the conductive lines even as the overall decoder area is reduced.
Solution Approach 2:
The patent employs asymmetrical spacer configurations around the trench transistor gate electrode, with different spacer lengths on opposite sides. This asymmetry allows for optimized control of the conductive line biasing, improving the precision of voltage application to memory cells while maintaining compact dimensions.
3Area of stationary object
If trench transistor gate electrode length is reduced, then area is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent forms the trench cavity in the substrate before depositing the gate electrode material. This preliminary action creates a physical template that guides and constrains the gate electrode formation, ensuring proper positioning and dimensions. The cavity acts as a pre-prepared structure that simplifies subsequent manufacturing steps and reduces precision requirements.
Solution Approach 2:
The trench cavity serves as an intermediary structure between the substrate and the gate electrode. It provides a defined space that mediates the relationship between these components, ensuring proper alignment and spacing without requiring extremely precise direct placement of the gate electrode on the substrate.
Data Source
AI summary
Methods, systems, and devices for memory device decoder configurations are described. A memory device may include an array of memory cells and decoder circuits. The array may include one or more memory cells coupled with an access line, and a decoder circuit may be configured to bias the access line to one or more voltages. The decoder circuit may include a first transistor coupled with the access line and a second transistor coupled with the access line. The first transistor may be a planar transistor having a first gate electrode formed on a substrate, and the second transistor may be a trench transistor having a second gate electrode that extends into a cavity of the substrate, where a length of a first gate electrode may be greater than a length of the second gate electrode.