Hybrid Memory Architecture Reducing Read Latency
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Solution Overview
Problem
Memory devices face high reading latency issues, which are costly to mitigate using low-density or expensive memory technologies like NOR Flash or SLC devices, while higher-density MLC or NAND Flash devices offer lower latency at higher costs.
Innovation Solution
The method involves dividing data into two parts and storing them in memory cells with different latency characteristics, such as NOR Flash cells for low latency and NAND Flash cells for higher latency, allowing the initial part to be read from low-latency cells and the second part concurrently from higher-latency cells, thereby reducing overall reading latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If low-density or expensive memory technologies like NOR Flash or SLC devices are used to reduce reading latency, then reading latency is reduced, but device cost increases
Solution Approach 1:
The memory device is segmented into two distinct memory regions: a first memory region using NOR Flash or SLC technology optimized for low-latency reads, and a second memory region using NAND Flash or MLC technology optimized for high-density storage. This segmentation allows the system to achieve low reading latency for frequently accessed data while maintaining cost-effectiveness for bulk storage, resolving the contradiction between speed and cost.
Solution Approach 2:
Different quality characteristics are assigned to different parts of the memory system. The first memory region employs high-performance, low-latency memory cells for critical data access paths, while the second region uses cost-effective, high-density memory cells for general storage. This local differentiation of quality enables the system to optimize for both speed and cost in appropriate locations.
2Ease of manufacture
If higher-density MLC or NAND Flash devices are used to reduce cost, then device cost is reduced, but reading latency increases
Solution Approach 1:
The memory device is segmented into two distinct memory regions: a first memory region using NOR Flash or SLC technology optimized for low-latency reads, and a second memory region using NAND Flash or MLC technology optimized for high-density storage. This segmentation allows the system to achieve low reading latency for frequently accessed data while maintaining cost-effectiveness for bulk storage, resolving the contradiction between speed and cost.
Solution Approach 2:
A memory management unit acts as an intermediary between the host system and the two memory regions. It intelligently manages data placement and access routing, directing read operations to the appropriate memory region based on data characteristics and access patterns. This intermediary enables the system to automatically optimize for low latency when needed while utilizing cost-effective high-density storage for less time-critical data.
Data Source
AI summary
A method for data storage includes providing a memory, which includes first memory cells having a first reading latency and second memory cells having a second reading latency that is higher than the first reading latency. An item of data intended for storage in the memory is divided into first and second parts. The first part is stored in the first memory cells and the second part is stored in the second memory cells. In response to a request to retrieve the item of data from the memory, the first part is read from the first memory cells and provided as output. The second part is read from the second memory cells, and provided as output subsequently to outputting the first part.