Hybrid NVM DRAM Memory Device with Integrated Capacitor
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Solution Overview
Problem
Conventional 3D NAND flash memory technologies face limitations in data transfer speed due to communication between nonvolatile memory (NVM) chips and random-access memory (RAM) chips, and they perform slow programming and erasing speeds due to single-page programming.
Innovation Solution
A hybrid memory system is developed that integrates volatile and nonvolatile memory devices in a stacking configuration, incorporating a drain select gate transistor and a capacitor component, enabling simultaneous data transfer and multi-page programming, and utilizing similar NAND strings for both DRAM and NAND flash memory functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional NVM and DRAM are fabricated in different dies and communicate via external bus, then device complexity is reduced, but data transfer speed deteriorates
Solution Approach 1:
The patent merges NVM and DRAM onto a single die, integrating nonvolatile memory cells and volatile memory cells in the same semiconductor device. This eliminates the external bus communication bottleneck by providing direct internal connection between NVM and DRAM, thereby improving data transfer speed while accepting increased fabrication complexity.
2Device complexity
If single-page programming is used in conventional NAND flash memory, then device complexity is reduced, but programming speed deteriorates
Solution Approach 1:
The patent segments the programming operation into multiple independent page-level units, allowing simultaneous programming of multiple pages through parallel operations. By organizing memory into multiple independently addressable pages that can be programmed concurrently, the system achieves multi-page programming capability that dramatically improves overall programming throughput.
Solution Approach 2:
The patent enables continuous programming operations by allowing multiple pages to be programmed in parallel without waiting for previous operations to complete. The memory controller can initiate programming of multiple pages simultaneously, maintaining continuous useful action and eliminating idle time associated with sequential single-page programming.
Data Source
AI summary
A memory system is configured to store information using a hybrid volatile and nonvolatile memory device. The memory system, in one aspect, includes memory components, a drain select gate (“DSG”) transistor, and a capacitor component. Each memory component, in one example, includes a source terminal, a gate terminal, a drain terminal, and a nonvolatile cell. The memory components are organized in a string formation and the components are interconnected between source terminals and drain terminals. The drain terminal of DSG transistor is coupled to the source terminal of a memory component and the gate terminal of DSG transistor is coupled to a DSG signal. The drain terminal of the capacitor is coupled to the source terminal of the first DSG transistor. The capacitor component is configured to perform a dynamic random-access memory (“DRAM”) function.