Hybrid Ring Chip Package Structure for Warpage Control
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Solution Overview
Problem
The challenge of forming a reliable chip package structure is exacerbated by the mismatch in thermal expansion coefficients between chips and wiring substrates, leading to package warpage and stress, which affects structural integrity and reliability, especially in advanced packaging technologies like CoWoS and InFO.
Innovation Solution
A hybrid ring and lid structure is introduced, comprising a first ring with low thermal expansion coefficient and high rigidity, combined with a second ring or anti-warpage lid of higher thermal expansion, creating a controlled stepwise warpage management system to mitigate stress and improve coplanarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a chip package structure includes chips and wiring substrate with different coefficients of thermal expansion, then the package can be formed with functional components, but package warpage and stress occur affecting structural integrity
Solution Approach 1:
The patent divides the package structure into distinct segments: a first ring structure with low CTE, a second ring structure with high CTE, and the wiring substrate. This segmentation allows each component to be optimized for its specific thermal expansion characteristics, managing the overall warpage through controlled differential expansion of the segmented rings rather than treating the package as a homogeneous structure.
Solution Approach 2:
The patent employs composite material principles by combining materials with different thermal expansion coefficients in a structured arrangement. The first ring structure uses a low CTE material while the second ring structure uses a high CTE material, creating a composite system that balances thermal stresses and controls warpage while maintaining structural integrity.
2Device complexity
If traditional single-structure approaches are used, then manufacturing is simpler, but package warpage and stress cannot be effectively controlled
Solution Approach 1:
The patent applies local quality by assigning different thermal expansion properties to specific locations within the package structure. The first ring structure (low CTE) and second ring structure (high CTE) are positioned at different locations to create localized thermal compensation zones, allowing precise control of warpage in critical areas while maintaining overall structural functionality.
Solution Approach 2:
The patent changes the thermal expansion parameter by introducing materials and structures with different CTE values. The first ring structure has a low CTE while the second ring structure has a high CTE, creating a stepwise gradient that actively manages thermal stress distribution and warpage control across the package structure.
3Reliability
If hybrid ring structure with different CTE materials is introduced, then warpage and stress are reduced, but structure complexity increases
Solution Approach 1:
The patent implements a nested structure where the first ring structure and second ring structure are arranged concentrically, with one ring positioned within or adjacent to the other. This nesting approach consolidates multiple functional elements into a compact hierarchical arrangement, reducing the overall spatial footprint and simplifying integration while maintaining the stress-mitigating benefits of differential CTE materials.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hybrid structure effectively reduces package warpage and stress, enhancing structural integrity and reliability of semiconductor packages, improving yield and performance.
Implementation Method 1
a first ring structure over the wiring substrate and surrounding the chip structure. A first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.
Data Source
AI summary
A chip package structure is provided. The chip package structure includes a wiring substrate. The chip package structure includes a chip structure over the wiring substrate. The chip package structure includes a first ring structure over the wiring substrate and surrounding the chip structure, wherein a first coefficient of thermal expansion of the first ring structure is less than a second coefficient of thermal expansion of the wiring substrate. The chip package structure includes an anti-warpage structure over the first ring structure. A third coefficient of thermal expansion of the anti-warpage structure is greater than the first coefficient of thermal expansion of the first ring structure.