Hybrid Seed Layer for On-Chip Inductor Eddy Currents
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Solution Overview
Problem
Conventional on-chip inductor fabrication techniques, such as 'bottom up' and damascene processes, face issues with uniformity and high resistance seed layers, leading to performance degradation and increased processing time, particularly for high frequency ferromagnetic inductor core structures.
Innovation Solution
A hybrid method using two seed layers: a low resistance seed layer for electroplating interconnects and a high resistance seed layer local to the magnetic core features, eliminating IR drop and eddy current-related performance issues without requiring additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high resistance seed layer is used local to the magnetic core features, then eddy current-related performance degradation is avoided, but IR drop occurs leading to uniformity issues during electrochemical deposition
Solution Approach 1:
The patent divides the seed layer into two distinct segments: a first seed layer with high resistance placed local to the magnetic core features to prevent eddy currents, and a second seed layer with low resistance positioned away from the magnetic core features to provide electrical connection and minimize IR drop. This segmentation allows each layer to perform its specific function without compromising the other.
Solution Approach 2:
The patent applies different resistance characteristics to different locations of the seed layer structure. The first seed layer has high resistance specifically where it contacts the magnetic core features to prevent eddy currents, while the second seed layer has low resistance in the interconnect region to minimize IR drop. This local differentiation of material properties resolves the contradiction between preventing eddy currents and maintaining uniform deposition.
2Manufacturing precision
If a low resistance seed layer is used for electroplating interconnects, then IR drop is minimized, but eddy current losses increase degrading high frequency performance
Solution Approach 1:
The patent segments the seed layer into two distinct layers with different resistance characteristics. The first seed layer (high resistance) is positioned local to the magnetic core features to prevent eddy currents, while the second seed layer (low resistance) is positioned away from the magnetic core features to provide low-impedance interconnects. This spatial segmentation resolves the contradiction between minimizing IR drop and preventing eddy current losses.
Solution Approach 2:
The patent assigns different electrical resistance properties to different spatial locations of the seed layer structure. The first seed layer has high resistance specifically at the interface with magnetic core features where eddy currents would occur, while the second seed layer has low resistance in the interconnect region where current flow requires low impedance. This local quality differentiation simultaneously addresses both requirements.
3Ease of manufacture
If conventional bottom up electroforming technique is used, then ferromagnetic structures are formed, but lengthy plating time and uniformity issues occur particularly with narrow aspect ratio features
Solution Approach 1:
The patent performs preliminary patterning of the first seed layer to define the magnetic core feature locations before electroforming the ferromagnetic structures. This preliminary action creates a precise template that guides the subsequent electroforming process, enabling faster and more uniform deposition compared to conventional bottom-up techniques that require longer plating times to achieve the same level of precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances high frequency device performance, reduces costs, and shortens processing time compared to conventional methods, enabling the fabrication of efficient on-chip inductor structures.
Implementation Method 1
a low resistance seed layer that provides the electroplating interconnects and that solves the IR drop problem
Implementation Method 2
a high resistance seed layer that is local to the magnetic core features thus avoiding eddy current related performance degradation
Implementation Method 3
The exposed portions of the seed layer 102 are then electroplated using conventional electrochemical deposition (ECD) techniques to provide the desired ferromagnetic structures 106
Implementation Method 4
By applying a current through the inductor, the magnetic flux is created
Data Source
AI summary
A hybrid method of fabricating magnetic core elements of an on-chip inductor structure addresses issues associated with conventional bottom up and damascene magnetic core plating techniques. The process uses two seed layers: a low resistance seed layer that solves the IR drop problem associated with the damascene plating techniques and a high resistance seed layer that is local to magnetic core features thus avoiding eddy current related performance degradation associated with the bottom up techniques.