Hybrid SOI Substrate Using Sacrificial Layer Cavities
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for hybrid SOI substrates that combine the advantages of both SOI and bulk semiconductor substrates, allowing for the integration of radio frequency devices on SOI regions and logic devices on bulk substrate regions on a single chip.
Innovation Solution
A method of manufacturing a hybrid SOI substrate involves forming a sacrificial layer over a semiconductor substrate, epitaxially growing an upper semiconductor layer, and then etching the sacrificial layer from a bulk substrate region to create a cavity beneath the upper semiconductor layer, which is then sealed with dielectric.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a full SOI substrate is used, then parasitic capacitances are reduced for high frequency circuits, but thermal management and noise reduction are compromised
Solution Approach 1:
The substrate is divided into distinct regions with different structures: SOI regions for high frequency circuits requiring low parasitic capacitance, and bulk substrate regions for logic devices requiring superior thermal management. This local differentiation allows each region to be optimized for its specific function without compromising the other.
Solution Approach 2:
The substrate is segmented into multiple functional regions including first SOI regions, second SOI regions, and bulk substrate regions. Each segment serves a specific purpose in the integrated circuit, enabling simultaneous optimization of electrical performance and thermal characteristics across different areas of the chip.
2Speed
If a full SOI substrate is used, then high frequency performance is improved, but integration of diverse device types on a single chip is limited
Solution Approach 1:
The hybrid substrate structure serves multiple functions simultaneously: it provides low parasitic capacitance for RF devices, excellent thermal management for logic devices, and supports both SOI and bulk-based device architectures on the same chip. This multi-functionality enables diverse device types to be integrated without requiring separate substrates.
Solution Approach 2:
Different regions of the substrate are tailored to specific device requirements: SOI regions with optimized thickness for high frequency performance, bulk regions for power and logic devices requiring thermal conductivity, allowing versatile device integration with each type operating in its optimal environment.
3Temperature
If bulk semiconductor substrates are used, then thermal management is improved, but parasitic capacitances increase affecting high frequency circuits
Solution Approach 1:
The substrate is segmented into bulk regions for thermal management and SOI regions for low parasitic capacitance, allowing each material structure to be used where it provides the greatest benefit rather than compromising a uniform design.
Solution Approach 2:
Bulk substrate material is applied locally in regions requiring thermal management, while SOI structure is applied in regions requiring low parasitic capacitance, creating a spatially optimized hybrid structure that addresses both requirements simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of hybrid SOI substrates that provide improved thermal management and noise reduction, while allowing for the integration of diverse device types on a single chip, enhancing overall performance and flexibility.
Implementation Method 1
The sacrificial layer is etched through holes that extend through a thickness of the upper semiconductor layer so as to define a cavity beneath the upper semiconductor layer
Implementation Method 2
An upper semiconductor layer is epitaxially grown over the sacrificial layer
Data Source
AI summary
A method of manufacturing a hybrid SOI substrate includes epitaxially growing a sacrificial layer and then an upper semiconductor layer over a semiconductor body. The sacrificial layer may be a heavily doped semiconductor. The heavy doping allows the sacrificial layer to be selectively etched while leaving the upper semiconductor layer largely intact. An SOI region of the semiconductor body is masked while the upper semiconductor layer and the sacrificial layer are etched from a peripheral region of the semiconductor body. A bulk semiconductor is then grown to replace the etched layers on the peripheral region. Holes are formed through the upper semiconductor layer in the SOI region and the sacrificial layer is etched from beneath the upper semiconductor. The holes may then be filled with dielectric leaving a cavity beneath the upper semiconductor layer in the SOI region.