A protective mask and selective etching correct tile placement and shape errors after bulk transfer, improving substrate alignment precision.
Zone-controlled outer-chamber gas exchange keeps wafer cooling uniform while maintaining a safe pressure difference to prevent leakage.
Controlled pressure, angle adjustment, and localized RF heating relieve residual stress to repair wafer bow and warp defects.
A sacrificial-layer SOI process creates RF SOI regions beside bulk logic regions on one chip, balancing low parasitics with thermal handling.
In-situ halogen etching and silane or germane surface conditioning remove dopant-rich SSLs to suppress arsine and phosphine outgassing.
Surface modification gas makes a hydrophilic wafer hydrophobic, preventing scanning liquid spread and improving metal contamination collection.
Reactive Se or Te annealing grows Cd(Se,Te) thin-film grains to millimeter scale, reducing voids and improving carrier diffusion for solar cells.
Misplaced substrate tiles are corrected by a protective mask and etching pattern that restores target geometry and alignment precision.
Selective etching of a heavily doped sacrificial layer forms SOI cavities and bulk regions on one substrate for RF performance and thermal management.
Reactive Se or Te annealing grows Cd(Se,Te) thin-film grains to millimeter scale, cutting grain boundaries and improving carrier transport.
Hydrogen-oxygen processing below 760 Torr generates oxygen radicals that improve oxide film uniformity, oxidation rate, and defect control.
Laser-formed defect arrays in the wafer surface absorb epitaxial stress, reducing warping and defects without added buffer layers.
DC chucking applied before gas and RF steps stabilizes bowed wafers, reducing plasma damage, backside defects, and defocus.
Trench-shaped transition layers are annealed into (111) single crystal surfaces, reducing GaN cracking from silicon lattice and thermal mismatch.
Radial temperature gradients reveal stress fields across wafer regions, enabling early screening of stress-optimized wafers before customer heat processes.
Laser-made internal defects and thermal stress from a receiving layer enable kerf-free solid layer splitting with lower TTV and less material waste.
Tubular PECVD rear-film deposition improves bifacial PERC passivation while reducing wafer scratching and undesirable deposition.
Zone-specific buffer gas exchange cools the annealing chamber faster while keeping pressure stable and thermal budgets uniform across zones.
Localized induction heating crystallizes semiconductor films on conductive flexible substrates, improving roll-to-roll quality and throughput.
Surface micro-oxidation and staged strip treatment cut eddy current loss while preserving magnetic shielding in wireless charging sheets.
Electrolyte exposure with induced current reduces the TCO surface, improving copper adhesion on ITO and lowering series resistance in solar cells.
Femtosecond laser zigzag processing forms a 40-80 μm amorphous layer in single-crystal SiC, cutting kerf loss while enabling clean separation.
Processing traces on a workpiece reveal laser astigmatism through aspect-ratio analysis, avoiding costly optical instruments and alignment.
Laser-formed modified layers and staged ultrasonic waves improve lithium tantalate wafer peel-off while reducing grindstone wear.
Combined microwave bulk heating and laser spot annealing improve large-wafer temperature uniformity, cut annealing time, and reduce cracks.
Selective mask exposure of laser-altered regions changes etch rates, enabling precise inner wall shaping in inorganic substrates.
Hot pressing pure cordierite composition minimizes secondary phases and pores, enabling mirror-flat substrates with stable thermal expansion.
Multiple double-sided texturing, diffusion, and laser grooving raise TOPCON bifaciality and efficiency while simplifying cell manufacturing.
Multiple double-sided texturing and laser grooving form mask-free localized emitters, improving bifacial TOPCON cell efficiency and lowering cost.