Semiconductor Wafer Thermal Treatment for Stress Field Detection

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Solution Overview

Problem

Existing processes for producing semiconductor wafers fail to effectively identify and mitigate stress fields across all regions of the wafer, leading to economic damage when these stress fields disrupt customer thermal processes.

Innovation Solution

A process involving the creation of a radial temperature gradient on semiconductor wafers during thermal treatment, using radially arranged heat sources to analyze and mitigate stress fields in the inner regions of the wafer, allowing for early identification and optimization of stress-free wafers before customer processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional thermal process simulation is used to identify stress fields, then stress fields at wafer edge can be detected, but stress fields in all regions of the wafer cannot be effectively identified

Engineering Contradiction:
Improvestress field detection capabilityVSAvoidcoverage of wafer regions
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The wafer is divided into multiple radial zones (inner region, middle region, outer region) with different temperature gradient applications. Each zone is analyzed separately for stress field formation, enabling comprehensive coverage of all wafer regions rather than just the edge area.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different temperature gradient conditions are applied to different radial zones of the wafer. The inner region receives a first temperature gradient while the middle and outer regions receive a second temperature gradient, allowing localized optimization of stress field detection for each region's specific characteristics.

Inventive Principle:
Principle #3Local quality

2Reliability

If comprehensive stress field analysis across all wafer regions is performed, then early identification of stress-free wafers is achieved, but additional thermal treatment steps and complexity are introduced

Engineering Contradiction:
Improvewafer quality assuranceVSAvoidthermal treatment process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Stress field analysis is performed during the manufacturing process before the wafer is delivered to the customer. By applying temperature gradients and analyzing stress fields in advance, defective wafers are identified and removed before customer thermal processes, preventing economic damage while maintaining process reliability.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The invention utilizes controlled temperature gradient parameters (first and second gradients in different radial zones) to induce and reveal stress fields. By adjusting these thermal parameters during analysis, the method achieves comprehensive stress detection without requiring complex additional equipment, balancing reliability with manageable process complexity.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enables the rapid and cost-effective identification of stress-optimized wafers, preventing economic losses by ensuring wafers conform to customer specifications, reducing the risk of stress-induced defects in customer thermal processes.

Implementation Method 1

a radial temperature gradient acts on the wafer

Methodology Applied
Scientific EffectTemperature gradient: Temperature Gradient

Implementation Method 2

thermal stresses in the crystal lattice. Stress-induced fields/stress fields

Methodology Applied
Scientific EffectThermal stress: Thermal Expansion

Data Source

PatentUS11972986B2Process for producing semiconductor wafers
Publication Date: 2024.04.30 SILTRONIC AG
  • US11972986B2 patent drawing
  • US11972986B2 patent drawing
  • US11972986B2 patent drawing

AI summary

Semiconductor wafers are produced by a process wherein a single-crystal ingot of semiconductor material is pulled and at least one wafer is removed from the ingot, wherein the wafer is subjected to a thermal treatment comprising a heat treatment step in which a radial temperature gradient acts on the wafer, wherein an analysis of the wafer of semiconductor material with respect to the formation of defects in the crystal lattice, so-called stress fields, is carried out.