Hybrid SOI Substrate Structure for RF and Logic Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for hybrid SOI substrates that combine the advantages of both SOI and bulk semiconductor substrates, particularly for integrating radio frequency devices on SOI regions and logic devices on bulk substrate regions, as existing technologies do not effectively facilitate this combination.
Innovation Solution
A method is developed to manufacture a hybrid SOI substrate by forming a sacrificial layer, epitaxially growing an upper semiconductor layer, etching and removing the sacrificial layer to create a cavity, and growing a bulk epitaxial layer, while using dielectric vias and STI structures to separate and insulate the regions, allowing for both SOI and bulk substrate regions on a single chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single substrate type is used for all devices, then manufacturing is simplified, but it is impossible to integrate both radio frequency devices requiring SOI substrates and logic devices requiring bulk substrates
Solution Approach 1:
The substrate is divided into distinct SOI regions and bulk substrate regions, allowing different device types to be integrated on separate areas of the same chip. The SOI region includes an upper semiconductor layer separated from the bulk substrate by an insulating layer, while the bulk substrate region maintains its conventional structure.
Solution Approach 2:
Different substrate structures are applied to different regions of the chip based on local device requirements. The SOI region provides low parasitic capacitance for radio frequency devices, while the bulk substrate region provides appropriate thermal and electrical characteristics for logic devices.
2Reliability
If SOI substrate is used for radio frequency devices, then parasitic capacitances are reduced improving high frequency performance, but thermal management becomes more difficult compared to bulk substrates
Solution Approach 1:
The chip is segmented into SOI regions for radio frequency devices and bulk substrate regions for logic devices, allowing each region to operate under its optimal thermal and electrical conditions while sharing the same physical chip.
3Adaptability or versatility
If hybrid SOI substrate with multiple regions is created, then both radio frequency and logic devices can be integrated, but the manufacturing process becomes more complex
Solution Approach 1:
The insulating layer is formed between the upper semiconductor layer and bulk substrate before device fabrication begins. This preliminary insulation structure is established through epitaxial growth or deposition processes that create the SOI region boundaries before any device-specific processing occurs.
Solution Approach 2:
The insulating layer acts as an intermediary between the upper semiconductor layer and bulk substrate, providing electrical isolation that enables the hybrid structure to function. This intermediate layer facilitates the integration of different device types by preventing unwanted electrical interactions between regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the integration of radio frequency and logic devices on a single chip, providing improved thermal management and noise reduction, while maintaining low parasitic capacitances and efficient device performance.
Implementation Method 1
An upper semiconductor layer is epitaxially grown over the sacrificial layer
Implementation Method 2
A bulk epitaxial layer is grown in the logic region so as to replace the layers that were etched away
Data Source
AI summary
A method of manufacturing a hybrid SOI substrate includes epitaxially growing a sacrificial layer and then an upper semiconductor layer over a semiconductor body. The sacrificial layer may be a heavily doped semiconductor. The heavy doping allows the sacrificial layer to be selectively etched while leaving the upper semiconductor layer largely intact. An SOI region of the semiconductor body is masked while the upper semiconductor layer and the sacrificial layer are etched from a peripheral region of the semiconductor body. A bulk semiconductor is then grown to replace the etched layers on the peripheral region. Holes are formed through the upper semiconductor layer in the SOI region and the sacrificial layer is etched from beneath the upper semiconductor. The holes may then be filled with dielectric leaving a cavity beneath the upper semiconductor layer in the SOI region.