Hybrid Substrate Tiling for Lower-Loss Electronic Interconnects
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Solution Overview
Problem
Existing electronic devices face challenges in achieving high reliability and quality while reducing costs and improving process yield, particularly in developing thin and light designs where complex circuit layouts and high-density interconnects are costly and prone to signal loss.
Innovation Solution
The implementation of a hybrid substrate comprising a first circuit substrate, multiple second circuit substrates, an interlayer, and electrical connection units with through holes and conductive materials, which reduces the number of substrate layers, simplifies circuit layouts, and allows for shorter signal transmission distances, thereby improving yield and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If complex circuit layouts and high-density interconnects are used to achieve thin and light designs, then device functionality is improved, but manufacturing cost increases and process yield decreases
Solution Approach 1:
The patent divides the circuit substrate into multiple separate substrates (first circuit substrate, second circuit substrate, third circuit substrate) that are stacked and interconnected. This segmentation allows each substrate to be manufactured independently with simpler circuits, avoiding the need for complex high-density interconnects on a single substrate, thereby reducing manufacturing cost and improving yield while maintaining thin and light device characteristics.
2Adaptability or versatility
If complex circuit layouts and high-density interconnects are used to achieve thin and light designs, then device functionality is improved, but process yield decreases
Solution Approach 1:
By segmenting the circuit into multiple substrates with simpler individual layouts, each substrate can be manufactured with higher yield. The modular approach allows independent fabrication and testing of each substrate layer, reducing the cumulative defect rate that would occur in a single complex substrate, thereby improving overall process yield while achieving the required device functionality.
3Reliability
If multiple substrate layers are stacked to reduce signal transmission distance, then signal loss is reduced, but device complexity increases
Solution Approach 1:
The patent segments the circuit functionality across multiple substrate layers, placing related circuit components on adjacent layers and connecting them through vertical interconnects. This reduces the lateral signal transmission distance within each substrate while maintaining a manageable overall structure through systematic layering and interconnection patterns.
Solution Approach 2:
The patent transitions from planar circuit layouts to a three-dimensional stacked architecture. By moving circuit components into the vertical dimension across multiple substrate layers and using through-substrate vias for interconnection, the patent reduces signal transmission paths while organizing complexity in a structured vertical arrangement rather than a congested planar layout.
Data Source
AI summary
The disclosure provides an electronic device and a tiled electronic device. The electronic device includes a hybrid substrate. The hybrid substrate includes a first circuit substrate, multiple second circuit substrates, an interlayer, and multiple electrical connection units. The first circuit substrate has a first surface and a second surface. The multiple second circuit substrates are disposed on the first surface. The interlayer is disposed between the multiple second circuit substrates and the first circuit substrate. The multiple electrical connection units penetrate the multiple second circuit substrates respectively. At least one electrical connection unit among the plurality of electrical connection units includes a through hole and a conductive material disposed in the through hole. At least one electrical connection unit is electrically connected to the first circuit substrate. The electronic device and the tiled electronic device according to the disclosure can improve process yield or save costs.