Hybrid Virtual GPIO Architecture for Inter-Processor Communication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The need for a large number of GPIO pins for inter-processor communication (IPC) and messaging signals in microprocessor systems increases manufacturing costs and limits availability for other system-level interfaces, as conventional approaches require dedicated pins for both GPIO and messaging signals.
Innovation Solution
A hybrid virtual GPIO architecture that uses a pair of pins to transmit and receive both GPIO and messaging signals, employing a finite state machine to differentiate between signal types and serialize them over a dedicated transmit and receive pin, reducing the overall number of pins required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated GPIO pins are used for each symmetric sideband signal, then reliable inter-processor communication is achieved, but the number of required pins increases significantly (n*2 GPIOs for n signals)
Solution Approach 1:
The patent applies universality by enabling a single messaging interface to perform multiple functions: it can transmit both traditional messaging signals with address headers and GPIO-like signals without address headers. The messaging interface is configured to recognize signal types and route them appropriately, allowing one physical interface to replace multiple dedicated GPIO pins while maintaining reliable communication for multiple symmetric sideband signals
2Adaptability or versatility
If dedicated transmit and receive pins are used for messaging signals, then messaging functionality is achieved, but manufacturing cost increases and pin availability for other interfaces is reduced
Solution Approach 1:
The patent merges the messaging interface and GPIO interface into a single hybrid interface. The messaging interface is enhanced to handle both messaging signals (with address headers) and GPIO signals (without address headers) through the same physical transmit and receive pins. This consolidation eliminates the need for separate dedicated pins for messaging, reducing manufacturing cost and increasing pin availability for other system-level interfaces
3Productivity
If multiple GPIO pins are allocated for IPC communication, then sufficient communication channels are provided, but GPIO availability for other system-level peripheral interfaces is limited
Solution Approach 1:
The messaging interface is designed with universal functionality to handle both messaging protocols and GPIO signaling. By configuring the messaging interface to recognize and process GPIO-like signals (identified by absence of address headers), the system achieves high IPC communication capacity without consuming dedicated GPIO pins, thereby maintaining GPIO availability for other peripheral interfaces
Data Source
Figure 1
Figure 2A~2B
Figure 3
AI summary
A finite state machine (115) is provided that both serializes virtual GPIO signals (135) and messaging signals (136) and that deserializes virtual GPIO signals and the messaging signals. The finite state machine frames the serialized virtual GPIO signals and messaging signals into frames each demarcated by a start bit and an end bit.