Hybrid Von-Neumann Dataflow Processor Architecture
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Solution Overview
Problem
Dataflow architectures face challenges in implementing control flow speculation and intercommunication of data values, making them inefficient for general computing tasks compared to Von Neumann architectures, and compiling arbitrary Von Neumann programs into dataflow programs is complex.
Innovation Solution
A hybrid Von Neumann/dataflow architecture that dynamically switches between execution modes on a general-purpose processor and a dataflow processor, allowing specific portions of an application program to be executed on the dataflow processor for improved performance and power efficiency, while using a prediction table to optimize execution based on execution benefits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dataflow architecture is used for general computing tasks, then processing speed is improved through instruction level parallelism, but control flow speculation becomes difficult to implement and intercommunication between functional units becomes costly
Solution Approach 1:
The system divides the computing task into segments that can be executed on different architectures. The hybrid processor separates instruction execution into dataflow-compatible portions (executed on dataflow functional units) and control-flow-intensive portions (executed on the Von Neumann processor), allowing each segment to leverage the strengths of its designated architecture while avoiding their weaknesses
Solution Approach 2:
A translation layer or intermediary mechanism is introduced between the Von Neumann instruction stream and the dataflow execution engine. This intermediary translates suitable instructions into dataflow operations while managing the complexity of control flow speculation and intercommunication, thereby enabling dataflow processing without directly exposing its complexity to the programmer or compiler
2Productivity
If arbitrary Von Neumann programs are compiled as dataflow programs, then instruction level parallelism is achieved, but compilation complexity increases significantly
Solution Approach 1:
Instead of attempting to convert entire programs to dataflow form, the system applies dataflow compilation selectively to specific regions or basic blocks of code that exhibit suitable characteristics (e.g., loops with regular data dependencies, computation-intensive sections). This local application reduces compilation complexity while still achieving instruction level parallelism where beneficial
Solution Approach 2:
The compilation process applies partial transformation, converting only the portion of the program that benefits from dataflow execution rather than the entire program. This partial action approach balances the benefits of parallelism against the costs of compilation complexity by being selective about which code regions undergo dataflow translation
3Use of energy by stationary object
If hybrid architecture switches between execution modes, then power efficiency is improved for specific program portions, but switching overhead between processors increases
Solution Approach 1:
The system performs preliminary analysis during compilation or runtime to identify and mark code regions suitable for dataflow execution. By pre-characterizing these regions, the hybrid processor can make faster switching decisions without extensive runtime analysis, reducing the overhead associated with mode transitions while still achieving power efficiency benefits
Data Source
AI summary
A dataflow computer processor is teamed with a general computer processor so that program portions of an application program particularly suited to dataflow execution may be transferred to the dataflow processor during portions of the execution of the application program by the general computer processor. During this time the general computer processor may be placed in partial shutdown for energy conservation.