Hydrophilic Polymer Protection Layer for Low-k Dielectric Integrity
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Solution Overview
Problem
Low dielectric constant (k) dielectric layers in electronic device packages are prone to damage from thermal or mechanical stress, have poor adhesion, and are susceptible to moisture absorption, leading to integrity issues during wafer bonding and electro plating processes.
Innovation Solution
A hydrophilic polymer protection layer with high mechanical strength is applied to the sidewalls of through holes and low k dielectric layers, providing moisture barrier and mechanical stress buffering, thereby enhancing the reliability and durability of the electronic device package structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If low k dielectric layer is used to minimize parasitical capacitance, then parasitical capacitance is reduced, but adhesion characteristics and mechanical strength deteriorate
Solution Approach 1:
The patent applies composite materials by combining low k dielectric layer with a silane-based protection layer having different mechanical properties. The protection layer has higher Young's modulus and better adhesion than the low k dielectric layer, creating a composite structure that provides both low parasitical capacitance and mechanical strength. The protection layer acts as a reinforcing phase that compensates for the mechanical weaknesses of the low k dielectric material.
2Loss of energy
If low k dielectric layer is used to minimize parasitical capacitance, then parasitical capacitance is reduced, but resistance to thermal and mechanical stress deteriorates
Solution Approach 1:
The patent implements beforehand cushioning by forming a silane-based protection layer on the low k dielectric layer before subsequent processing steps. This protection layer serves as a cushion that absorbs and distributes thermal and mechanical stresses, preventing direct stress transmission to the fragile low k dielectric layer. The protection layer is specifically designed to withstand electro plating and thermal bonding processes that would otherwise damage the low k dielectric material.
3Loss of energy
If low k dielectric layer is used to minimize parasitical capacitance, then parasitical capacitance is reduced, but moisture absorption increases
Solution Approach 1:
The patent uses an silane-based protection layer as an intermediary between the low k dielectric layer and the external environment. This protection layer acts as a moisture barrier that prevents water molecules from reaching and absorbing into the low k dielectric layer. The silane-based material forms a hydrophobic barrier that blocks moisture penetration while allowing the underlying low k dielectric layer to maintain its electrical properties.
4Strength
If conventional protection methods are used during wafer bonding, then adhesion is improved, but low k dielectric layer integrity deteriorates due to moisture absorption
Solution Approach 1:
The silane-based protection layer serves as a dual-function intermediary that simultaneously provides adhesion enhancement and moisture protection. During wafer bonding, this protection layer adheres to both the low k dielectric layer and the bonding substrate, ensuring strong adhesion. At the same time, it forms a moisture barrier that prevents water absorption during wet electro plating and thermal bonding processes, thereby maintaining the integrity of the low k dielectric layer throughout the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The hydrophilic polymer protection layer effectively prevents moisture absorption and mechanical stress-induced failures, maintaining the integrity of low k dielectric layers throughout wafer drilling, cutting, and bonding processes, improving the reliability and durability of the electronic device package.
Implementation Method 1
A hydrophilic polymer protection layer covers the dielectric layer and sidewalls of the trench
Data Source
AI summary
The invention provides an electronic device package structure and method of fabrication thereof. The electronic device package structure includes a chip having an active surface and a bottom surface. A dielectric layer is disposed on the active surface of the chip. At least one trench is formed through the dielectric layer. A first protection layer covers the dielectric layer and sidewalls of the trench. A second protection layer covers the first protection layer, filling the trench.


