Hyper-abrupt Junction Superlattice for Carrier Mobility
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Solution Overview
Problem
Current semiconductor devices face limitations in enhancing charge carrier mobility and performance due to issues such as alloy scattering and diffusion between thin layers, which affect device efficiency and mobility.
Innovation Solution
The implementation of a hyper-abrupt junction region with a superlattice structure, comprising stacked semiconductor and non-semiconductor monolayers, which reduces effective mass and enhances conductivity, and includes a gate dielectric layer and gate electrode to improve charge carrier mobility and block diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If thin semiconductor layers are used to enhance carrier mobility, then device performance is improved, but diffusion between layers occurs causing performance degradation
Solution Approach 1:
A superlattice barrier layer is introduced between the n-type and p-type semiconductor layers. This superlattice structure acts as an intermediary that prevents dopant diffusion between adjacent layers while maintaining the thin-layer configuration needed for high carrier mobility. The superlattice serves as a diffusion barrier without requiring thicker isolation layers that would degrade device performance.
2Speed
If alloy scattering is reduced to improve mobility, then carrier mobility increases, but device complexity increases due to superlattice structure
Solution Approach 1:
The superlattice barrier layer is applied locally only at the junction region where diffusion prevention is critical, rather than throughout the entire device. This localized application reduces the overall complexity increase while providing the necessary diffusion barrier function. The superlattice structure is confined to where it is most needed - at the interface between oppositely doped regions.
3Speed
If hyper-abrupt junction with superlattice is implemented to reduce ionized impurity scattering, then charge carrier mobility is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The barrier layer is segmented into a superlattice structure consisting of multiple thin alternating layers rather than a single thick layer. This segmentation allows for better control of the overall barrier thickness and composition, as each individual layer can be grown with standard precision while the cumulative effect achieves the desired diffusion barrier properties. The segmented superlattice structure is more tolerant to manufacturing variations than a single critical-thickness layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in higher charge carrier mobility, reduced ionized impurity scattering, and improved device performance by maintaining a direct energy bandgap, suitable for opto-electronic devices and other applications.
Implementation Method 1
U.S. Pat. No. 5,357,119 to Wang et al. discloses a Si—Ge short period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice
Implementation Method 2
The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions
Implementation Method 3
U.S. Pat. No. 6,472,685 B2 to Takagi discloses a semiconductor device including a silicon and carbon layer sandwiched between silicon layers so that the conduction band and valence band of the second silicon layer receive a tensile strain. Electrons having a smaller effective mass, and which have been induced by an electric field applied to the gate electrode, are confined in the second silicon layer
Implementation Method 4
U.S. Patent Application No. 2003/0057416 to Currie et al. discloses strained material layers of silicon, silicon-germanium, and relaxed silicon and also including impurity-free zones that would otherwise cause performance degradation. The resulting biaxial strain in the upper silicon layer alters the carrier mobilities enabling higher speed and/or lower power devices
Implementation Method 5
The implementation of a hyper-abrupt junction region with a superlattice structure, comprising stacked semiconductor and non-semiconductor monolayers, which reduces effective mass and enhances conductivity, and includes a gate dielectric layer and gate electrode to improve charge carrier mobility and block diffusion
Data Source
AI summary
A semiconductor device may include a substrate and a hyper-abrupt junction region carried by the substrate. The hyper-abrupt junction region may include a first semiconductor layer having a first conductivity type, a superlattice layer on the first semiconductor layer, and a second semiconductor layer on the superlattice layer and having a second conductivity type different than the first conductivity type. The first, second, and the superlattice layers may be U-shaped. The semiconductor device may further include a gate dielectric layer on the second semiconductor layer of the hyper-abrupt junction region, a gate electrode on the gate dielectric layer, and spaced apart source and drain regions adjacent the hyper-abrupt junction region.