3D Hyperchip Assembly Using Active Die Interposer Architecture
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Solution Overview
Problem
Modern integrated circuit packaging techniques face challenges in maximizing die-to-die connections, leading to complex layouts and depressed yield rates due to traditional 2.5D solutions using silicon interposers and through silicon vias (TSVs).
Innovation Solution
The implementation of hyperchip structures with an active interposer die that enables three-dimensional stacked arrangements, allowing for heterogeneous integration of multiple circuit functions and efficient die-to-die connections through through silicon vias (TSVs) and microbumps, facilitating high-density and high-performance processing while maintaining a smaller footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional 2.5D solutions using silicon interposers and through silicon vias (TSVs) are used to maximize die-to-die connections, then connection density and speed are improved, but layout complexity and manufacturing complexity increase, depressing yield rates
Solution Approach 1:
The patent transitions from 2.5D interposer-based connections to true 3D stacked die architecture, where multiple dies are vertically stacked and connected through microbumps and TSVs. This dimensional change eliminates the need for separate silicon interposers, reducing layout complexity while maintaining high connection density through vertical stacking.
Solution Approach 2:
The patent merges the functions of the silicon interposer and the active die into a single integrated structure. The active die serves both as a functional component and as the interconnection substrate, eliminating the need for a separate passive interposer layer and simplifying the overall manufacturing process.
2Reliability
If traditional 2.5D solutions with silicon interposers are used, then die-to-die connections are achieved, but manufacturing yield decreases due to increased complexity
Solution Approach 1:
The patent performs preliminary integration by forming TSVs and interconnect structures on the active die before die stacking. This advance preparation allows for more controlled and reliable connections during the stacking process, improving manufacturing yield by reducing the complexity of post-assembly operations.
Solution Approach 2:
By moving to 3D stacking, the patent reduces the number of lateral connection paths required, simplifying the interconnection architecture. This dimensional transition from 2.5D to 3D reduces manufacturing steps and improves yield by eliminating the need for complex lateral routing through separate interposer layers.
3Adaptability or versatility
If heterogeneous integration of multiple circuit functions is implemented in 3D stacked arrangement, then functionality and performance are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent segments different circuit functions into separate dies that are then stacked vertically. Each die can be optimized for its specific function (e.g., logic, memory, I/O) and manufactured using appropriate processes, then integrated through standardized TSV and microbump interfaces. This segmentation enables heterogeneous integration while maintaining manageable manufacturing complexity through modular assembly.
Solution Approach 2:
The active die serves multiple functions simultaneously: it performs its primary circuit function, provides the interconnection substrate for stacking, and hosts the TSV structures for vertical connections. This multi-functionality reduces the need for separate dedicated interposer structures, simplifying manufacturing despite the heterogeneous nature of the integrated system.
Data Source
AI summary
Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.